Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/01—Modifications for accelerating switching
  • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
  • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

• the present invention relates generally to a CMOS input buffer for semiconductor devices.
• CMOS Complementary metal oxide semiconductor
• FIG. 1 illustrates an example of a conventional CMOS inverter input buffer 100 for semiconductor devices.
• the CMOS inverter input buffer 100 includes a P-channel MOSFET transistor 106, also called a
• the PMOS transistor, and an N-channel MOSFET transistor 108 also called an NMOS transistor in a complementary configuration.
• the gates of the PMOS and NMOS transistors 106, 108 are connected with the input node 102, also called the input terminal. Because both gates are connected with the input node 102, the input signal is also called the gate voltage, Vg.
• the output signal is transmitted from the output node 110, also called the output terminal.
• the output node 110 is connected with the drains of the PMOS and the NMOS transistors 106, 108. When a low signal, substantially zero volts, is applied to the input node 102, the PMOS transistor 106 is turned on and the NMOS transistor 108 is turned off, driving the output node 110 high.
• the PMOS 106 transistor When a high signal, substantially the supply voltage, is applied to the input terminal 102, the PMOS 106 transistor is turned off and the NMOS transistor 108 is turned on driving the output node low. Since one of the PMOS and NMOS transistors is in the off state, little if any DC current is consumed.
• FIG. 2 illustrates an example of a conventional CMOS NOR input buffer 200.
• the CMOS NOR input buffer 200 includes first and second PMOS transistors 210, 212, and first and second NMOS transistors 214, 216.
• the gates of the second PMOS transistor 212 and the first NMOS transistor 214 are connected with the input node 202.
• the output signal is transmitted from the output node 210 connected with the drains of the second PMOS transistor 212 and the first and second NMOS transistors 214, 216.
• the control signal "power down" is received at the control node 218.
• the control node 218 is connected with the gates of the first PMOS transistor 210 and the second NMOS transistors 216.
• An input buffer circuit for a semiconductor device that includes a PMOS transistor, an NMOS transistor, and a pull-up circuit.
• the pull-up circuit applies a voltage to the bulk region of the PMOS transistor causing a positive body effect that temporally lowers the absolute value of the voltage threshold of the PMOS transistor when the input buffer switches. This causes the input buffer to switch faster than convention input buffers.
• the input buffer is an inverter, NOR, NAND, or other input buffer.
• FIG. 1 is an illustration of a conventional CMOS inverter input buffer
• Figure 2 is an illustration of a conventional CMOS NOR input buffer
• Figure 3 is an illustration of an embodiment of the present invention relating to a CMOS inverter input buffer
• Figure 4 is an illustration of an embodiment of the present invention relating to a CMOS NOR input buffer
• Figure 5 is an illustration of a cross-sectional view of a PMOS transistor embodying elements of the present invention.
• An input device for semiconductor devices such as memory devices like SRAM and DRAM, provides fast switching between high and low output states.
• the input device operates at low supply voltages with low current leakage.
• the present invention temporarily lowers the absolute value of the threshold voltage to reduce the switching time without creating substantial current leakage.
• An input buffer monitors an input node for a signal and switches an output node based on the input node. While the input buffer and the circuits beyond the output node operate between a supply voltage, Vcc, and ground, the signals received at the input may be in a narrower range, for example Vih and Vil. Vih represents a "High” signal and Vil represent a “Low” signal. As a result of line capacitance and other factors, Vil is often higher than ground and Vih is often lower then the supply voltage.
• the PMOS transistors tend to switch at even slower rates when operated at low supply voltage.
• Low supply voltages are supply voltages below 3.3 volts, such as 1.8 volts or 1.6 volts. In many applications it is desirable to have switches operate as quickly as possible.
• CMOS transistors are "weaker” than NMOS transistors. This is due to the mobility factor. Because the absolute value of the threshold voltage,
• the threshold voltage is used to determine if the signal on an input line is high or low. If the absolute value of the threshold voltage of a PMOS transistor is lowered in an attempt to reduce the switching speed, the current leakage in the PMOS transistor will increase, which is undesirable.
• the present invention temporarily lowers the absolute value of the threshold voltage to reduce the switching time without creating substantial current leakage and is illustrated in Figures 3-5.
• FIG. 3 illustrates an example of a CMOS inverter input buffer 300 with fast switching and low current leakage.
• the CMOS inverter input buffer 300 includes a PMOS transistor 306, an NMOS transistor 308 in a complementary configuration, a pull-up device 314, and an optional capacitor 312.
• the gates of the PMOS and NMOS transistors 306, 308 are connected with the input node 302.
• the output signal is transmitted from the output node 310, which is connected with the drains of the PMOS and the NMOS transistors 306, 308.
• a pull-up device 314, for example a resistor, is connected with the supply voltage and the bulk of the PMOS transistor 306.
• the resistance of the pull-up device 314 depends on the characteristics of the input buffer 300 and in particular it depends on the characteristics of the PMOS transistor 306. For example, the resistance value can be 1 KOhm to 3000 KOhms. Other pull-up devices 314 can be used as long as they provide voltage to the bulk region of the PMOS transistor, for example a RL circuit, a diode, or other device.
• the pull-up device 314 acts as a charging mechanism for supplying a voltage to a bulk of the PMOS transistor 306.
• An optional capacitor 312 is connected with the gate and the bulk of the PMOS transistor.
• the capacitor 312 adds gate capacitance to the input buffer 300 when the PMOS and NMOS transistors 306, 308 do not provide sufficient input capacitance to increase the buffer's switching time.
• FIG. 4 illustrates an example of a CMOS NOR input buffer 400 with fast switching and low leakage current.
• the CMOS NOR input buffer 400 includes first and second PMOS transistors 410, 412, first and second NMOS transistors 414, 416, first and second pull-up devices 406, 408, and an optional capacitor 422.
• the gates of the second PMOS transistor 412 and the first NMOS transistor 414 are connected with the input node 402.
• the output signal is transmitted from the output node 420, which is connected with the drain of the second PMOS transistor 412 and the drains of the first and second NMOS transistors 414, 416.
• the sources of the first and second NMOS transistors 414, 416 are connected with ground.
• the source of the second PMOS transistor 412 is connected with the drain of the first PMOS transistor 410.
• the source of the first PMOS transistor 410 is connected with the supply voltage 404.
• the control signal labeled "power down", is received at the control node 418.
• the control signal is connected with the gates of the first PMOS transistor 410 and the second NMOS transistor 416.
• the control node 418 and the input node 402 are the inputs to the
• a first pull-up device 406 is connected with the supply voltage and the bulk of the first PMOS transistor 410.
• the second pull-up device 408, also called a pull-up circuit, is connected with the supply voltage 404 and the bulk of the second PMOS transistor 412.
• the resistance of the pull-up devices 406, 408 depend on the characteristics of the input buffer 400 and depend in particular on the characteristics of the
• the resistance of the pull-up devices 406, 408 can be 1 KOhms to 3000 KOhms. Other values are also acceptable depending on the characteristics of the input buffer 400.
• the pull-up devices 406, 408 can include other circuits as long as the circuits provides voltage to the bulk region of the PMOS transistors 410, 412, for example a RL circuit, a RLC circuit, a diode circuit, or other device.
• the pull-up devices 406, 408 in this embodiment act as a charging means for supplying a voltage to a bulk of the PMOS transistors 410, 412. In another embodiment, only one of the two pull-up devices 406, 408 is used.
• An optional capacitor 422 can be added to increase the gate capacitance. The optional capacitor 422 is connected with the gate and the bulk of the second PMOS transistor 412.
• the first PMOS transistor 410 and the pull-up devices 406, 408 are each connected with different supply voltages.
• Traditional supply voltages are 5.0 volts and 3.3 volts.
• the present invention is preferably used with low power input buffers.
• Low power input buffers have supply voltages of 3.3 volts or less.
• the supply voltage can be approximately 2.0 volts to 1.0 volts.
• the present invention could also be used with other supply voltage ranges.
• FIG. 5 is a cross-sectional view of a PMOS transistor 500 embodying elements of the present invention.
• the PMOS transistor 500 includes an N-type substrate region 526, a dielectric region 524, two P- type regions 518, 522, and a P-channel region 520, also called an N-well region.
• the PMOS transistor's 500 external interfaces include a source 512, a gate 514, a drain 516, and a bulk 528.
• the PMOS transistor 500 has a pull-up device 506 connecting the bulk 528 with the supply voltage at the source node 504.
• An optional capacitor 508 connects the bulk 528 with the gate 514.
• the gate 514 is connected with a gate node 502 that receives the gate signal.
• the drain 516 is connected with the drain node 510 that transmits the output from the PMOS transistor 500. When ground, substantially zero volts, is applied to the gate node 502, no P-channel 520 is created and the drain 516 supplies minimal current. When a negative voltage is applied to the gate node
• the body effect phenomenon in an NMOS transistor occurs when the potential difference between the back-gate voltage, Vb, and the source potential, Vs, called Vbs, is negatively changed by the voltage of an input signal and increases the absolute value of the threshold voltage of the NMOS transistor.
• Vb back-gate voltage
• Vs source potential
• the potential difference Vbs is positively changed to increase the absolute value of the threshold voltage.
• the gate to source voltage, Vgs decreases
• the driving ability of the NMOS transistor decreases, and the signal transfer resistance increases. This is known as a "negative" body effect.
• the present invention uses a complementary phenomena called a "positive" body effect to temporarily lowers the absolute value of the voltage threshold of a PMOS transistor.
• the input buffers 300 ( Figure 3), 400 ( Figure 4) described above have a high DC threshold voltage that results in a lower leakage voltage. Additionally, the input buffers 300, 400 have low AC threshold voltages that provide faster switching and lower leakage voltage. It is estimated that such an input buffer could switch from high to low in about 50% to 60% of the time of a conventional low voltage input buffer.
• the input buffer 500 can be used with a variety of devices including semiconductor memory for use in a computer, cellular telephone flash memory, logic circuits, and other circuits. In a preferred embodiment, the input buffer 500 is used with low power semiconductor memory. When an input line transitions from high to'low, from logic 1 to logic 0, the gate capacitance is pulled down momentarily. This causes the absolute value of the threshold voltage to decrease.
• Vbulk The voltage at the bulk layer, Vbulk, is charged back to full supply voltage through the pull-up device 506 after the output node 510 has switched to high.
• a capacitor 508 is added to increase the gate to bulk capacitance.
• is the absolute value of the threshold voltage of the PMOS transistor.
• ⁇ p is the bulk potential.
• the bulk potential is a function of the fabrication process and can vary between devices.
• the RC circuit for example 506 and 508 ( Figure 5), preferably is scaled to avoid a latch-up condition •when the bulk voltage is less than the source voltage.
• Figures 3 to 5 illustrate an inverter and an NOR input buffer
• the present invention can be implemented with other input buffer used for semiconductor devices, such as memory devices.
• the present invention can be used with an NAND input buffer.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Logic Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2001
  • 2001-06-29 WO PCT/US2001/020818 patent/WO2002007317A1/en not_active Ceased
  • 2001-06-29 EP EP01950703A patent/EP1307965A1/de not_active Withdrawn
  • 2001-06-29 KR KR10-2003-7000515A patent/KR20030016401A/ko not_active Withdrawn
  • 2001-06-29 AU AU2001271671A patent/AU2001271671A1/en not_active Abandoned
  • 2001-06-29 JP JP2002513098A patent/JP2004504751A/ja not_active Withdrawn
  • 2001-06-29 CN CN01812668A patent/CN1441996A/zh active Pending
  • 2001-06-29 BR BR0112513-3A patent/BR0112513A/pt not_active Application Discontinuation
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