Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
  • H04L1/206—Arrangements for detecting or preventing errors in the information received using signal quality detector for modulated signals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/04—Distributors combined with modulators or demodulators
  • H04J3/047—Distributors with transistors or integrated circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/20—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Definitions

• the present invention relates generally to demultiplexing, hi particular, the present invention relates to methods and apparatus for receiving and demultiplexing electrical and optical signals.
• Optical receivers for optical fiber communication systems convert modulated optical signals received at the output end of the optical fiber into received electrical data signals.
• Optical receivers generally include a photodetector, an amplifier, a demodulator and other signal processing circuitry.
• a photodetector such as a photodiode, is optically coupled to the end face of the optical fiber.
• the photodetector converts the received modulated optical signal into an electrical data signal.
• the amplifier amplifies the received optical signal to a level that is large enough for electronic processing.
• the design of the demodulator depends on the modulation format used by the optical communication system, intensity modulated direct detection optical communication systems, the received signal is in the form of optical pulses representing 1 and 0 bits and it is converted directly into an electric current. Demodulation is typically done by a decision circuit that identifies bits as 1 or 0 depending on the amplitude of the electrical current. The accuracy of the decision circuit depends on the signal-to-noise ratio of the electrical signal generated by the photodetector.
• Optical Time-Division Multiplexing (OTDM) communication systems can transmit data in a single optical channel at ultra-high bit rates. Functionally OTDM is identical to electronic TDM. Bits associated with different channels are interleaved in the time domain to form a bit interleaved bit stream.
• OTDM transmitters multiplex several lower-speed optical bit streams modulated at bit rate R to form a bit interleaved optical bit stream modulated at bit rate RN, where N is the number of multiplexed optical channels.
• OTDM receivers receive the bit interleaved optical bit stream at bit rate NR and extract the lower-speed optical bit streams modulated at bit rate R.
• OTDM transmitters and receivers use high-speed multiplexing and demultipexing techniques.
• OTDM multiplexing is described in U.S. patent application serial number 09/566,303, entitled Bit Interleaved Optical Multiplexing, which is assigned to the current assignee. The entire disclosure of U.S. patent application serial number 09/566,303 is incorporated herein by reference.
• OTDM demultiplexers demultiplex individual channels from an OTDM signal.
• OTDM demultiplexers require a clock signal that is a periodic pulse train having a frequency that is harmonically related to a single channel bit rate.
• the clock signal is an electrical clock signal for electro-optic demultiplexing, and is an optical pulse train for all-optical demultiplexing.
• Some prior art demultiplexers are electro-optic and use Mach-Zehnder-type lithium niobate modulators. Each modulator in the demultiplexer halves the bit rate by rejecting alternate bits in the incoming signal.
• Other prior art demultiplxers are all-optical. State-of-the art OTDM receivers require all-optical demultiplexing because all-optical components are needed to process the high bit rates associated with the OTDM signals.
• One prior art all-optical demultiplxer uses nonlinear optical- loop mirrors constructed from a fiber loop whose ends are connected to two input ports of a fiber coupler. Still other prior art all-optical demultiplexers use four- wave mixing in a non-linear medium.
• the present invention relates to receivers and demultiplexers for electronic Time Division Multiplexed (TDM) and Optical Time Division Multiplexed (OTDM) communication systems.
• TDM Time Division Multiplexed
• OTDM Optical Time Division Multiplexed
• One advantage of demultiplexers and receivers of the present invention is that they are relatively simple and easy to implement.
• a demultiplexer of the present invention uses decision circuits for demultiplexing TMD and OTMD signals.
• the present invention features a demultiplexer for demultiplexing high-speed signals.
• the demultiplexer demultiplexes Time Division Multiplexed (TDM) signals.
• the demultiplexer includes an electrical splitter that separates an electrical TDM data signal into a plurality of electrical TDM data signals that propagate in a plurality of electrical transmission lines.
• a broadband filter may be coupled to at least one of the plurality of electrical transmission lines to filter noise from the TDM data signal. Filters may also be coupled to at least one of the plurality of electrical transmission lines to shape and broaden the pulse to increase more link margin.
• a clock recovery circuit generates a clock signal that is synchronized to the electrical TDM data signal and that has a frequency that is harmonically related to the TDM channel data rate. Harmonically related is defined herein to mean frequencies that are equal to the single channel TDM channel data rate, a sub-harmonic of the single TDM channel data rate, or an integer multiple of the single channel TDM channel data rate.
• the clock recovery circuit includes a harmonic mixer, phase detector, and a voltage controlled oscillator.
• the voltage controlled oscillator may be a dielectric resonator oscillator.
• a phase shifter adjusts the phase of the clock signal
• the demultiplexer includes a plurality of phase shifters.
• a respective one of the plurality of phase shifters is electrically coupled between the output of the clock recovery circuit and the clock input of a respective one of a plurality of decision circuits used for demultiplexing, h one embodiment, header and SONET information is used to control the state of the phase shifter.
• the demultiplexer also includes a plurality of decision circuits.
• Each of the plurality of decision circuits has a data input that is electrically coupled to one of the plurality of electrical transmission lines. The data input receives the electrical TDM data signal.
• Each of the plurality of decision circuits also has a clock input that is electrically coupled to an output of the clock recovery circuit. The clock input receives the clock signal.
• Each of the plurality of decision circuits generates demultiplexed TDM signals at a data output.
• the phase shifter is adjusted so that the desired data in each of the demultiplexed TDM signals is selected.
• header or SONET information is used to control the state of the phase shifter.
• the demultiplexer includes a feedback circuit that has an input electrically coupled to a data output of at least one of the plurality of decision circuits. An output of the feedback circuit is electrically coupled to a control input of the phase shifter.
• the feedback circuit generates a signal at the output that is related to the phase of the demultiplexed TDM signal generated by the decision circuit.
• the signal causes the phase shifter to adjust the phase of the clock signal propagated to the decision circuit so that the desired demultiplexed TDM data signal generated by the decision circuit is selected.
• the demultiplexer includes an error correction circuit that has an input that is electrically coupled to the data output of one of the plurality of decision circuits.
• the error correction circuit may be a forward error correction (FEC) circuit.
• the present invention also features a method of demultiplexing TDM data signals.
• the method includes splitting an electrical TDM data signal into a plurality of electrical TDM data signals.
• the electrical TDM data signal is derived from an OTDM data signal.
• the OTDM data signal may comprise a return- to-zero (RZ) OTDM data signal.
• the electrical TDM data signals may be filtered to reduce noise.
• a clock signal is generated that is synchronized to the electrical TDM data signal and that has a frequency that is harmonically related to a single TDM channel data rate.
• Each of the plurality of electrical data signals is propagated though one of a plurality of decision circuit that is clocked with the clock signal, thereby generating a plurality of demultiplexed TDM signals.
• a phase of the clock signal to at least one of the plurality of decision circuits is then adjusted so that desired data in at least one of the plurality of demultiplexed TDM signal is selected, h one embodiment, the phase of the clock signal to each of the plurality of decision circuits is adjusted so that each of the plurality of demultiplexed TDM signal is selected. Also, in one embodiment, the phase of the clock signal is adjusted by sampling a portion of the at least one of the plurality of demultiplexed TDM signals and adjusting the phase of the clock signal relative to an amplitude or BER of the sampled portion of the demultiplexed TDM signal.
• the present invention features an Optical Time Division Multiplexed (OTDM) receiver.
• the receiver includes a detector that is positioned to receive an OTDM data signal.
• the detector generates an electrical TDM data signal that is indicative of the OTDM data signal.
• the OTDM data signal is received from an optical fiber communication link.
• the detector comprises a photodiode having a bandwidth that is substantially greater than the bandwidth of the OTDM data signal.
• an amplifier is electrically coupled to an output of the detector. The amplifier amplifies the electrical TDM data signal to useful signal levels. Typically, the bandwidth of the amplifier is greater than the bandwidth of the electrical TDM data signal.
• the receiver includes an electrical splitter that separates an electrical TDM data signal into a plurality of electrical TDM data signals that propagate in a plurality of electrical transmission lines.
• a broadband filter may be coupled to at least one of the plurality of electrical transmission lines to filter noise from the TDM data signal.
• a clock recovery circuit generates a clock signal that is synchronized to the electrical TDM data signal and that has a frequency that is harmonically related to a single TDM channel data rate.
• the clock recovery circuit may include a harmonic phase detector.
• the clock recovery circuit may also include a dielectric resonator oscillator.
• a phase shifter adjusts the phase of the clock signal
• the receiver includes a plurality of phase shifters.
• a respective one of the plurality of phase shifters is electrically coupled between the output of the clock recovery circuit and the clock input of a respective one of a plurality of decision circuits.
• the receiver also includes a plurality of decision circuits.
• Each of the plurality of decision circuits has a data input that is electrically coupled to one of the plurality of electrical transmission lines. The data input receives the electrical TDM data signal.
• Each of the plurality of decision circuits also has a clock input that is electrically coupled to an output of the clock recovery circuit for receiving the clock signal.
• each of the plurality of decision circuits generates demultiplexed TDM signals at a data output. The phase shifter is adjusted so that the desired data in each of the demultiplexed TDM signals is selected.
• the receiver includes a feedback circuit that has an input electrically coupled to a data output of at least one of the plurality of decision circuits. An output of the feedback circuit is electrically coupled to a control input of the phase shifter.
• the feedback circuit generates a signal related to the phase of the demultiplexed TDM signal generated by the decision circuit and causes the phase shifter to adjust the phase of the clock signal propagated to the decision circuit so that the bit error rate is reduced.
• Fig. 1 illustrates an optical receiver that uses decision circuits according to the present invention.
• Fig. 2 illustrates a clock recovery circuit according to the present invention for the optical receiver of Fig. 1. Detailed Description
• Fig. 1 illustrates an optical receiver 10 that uses decision circuits according to the present invention.
• the receiver 10 includes a photodiode 12 that is in optical communication with an optical data source.
• the optical data source may be an optical RZ data source.
• the receiver 10 receives data transported though an optical fiber communication link, hi this embodiment, the photodiode 12 is in optical communication with the end face 14 of an optical fiber 16.
• the photodiode 12 converts the received optical data signal into an electrical data signal.
• the photodiode 12 typically has a response time that is fast enough to convert substantially all of the useful optical data to an electrical data signal.
• the converted electrical data signal is a relatively low-level signal.
• the converted electrical data signal contains substantial noise that may result in loss of data.
• An electronic amplifier 18 amplifies the electrical data signal to useful signal levels.
• the electronic amplifier 18 is a broadband electronic amplifier that has a bandwidth wide enough to capture substantially all of the useful electrical data.
• a RF coupler 20 samples a portion of the electrical data signal for clock recovery, one embodiment, the RF coupler 20 is a broadband optical coupler that passes substantially all of the useful data.
• a splitter 22 separates the electrical data signal into a first and a second electrical data signal that propagate in a first 24 and second electrical transmission lines 26, respectively.
• a first 28 and a second filter 30 is electrically coupled to each of the first 24 and the second waveguide 26, respectively.
• the first 28 and second filter 30 are broadband filters that reject high frequency noise that may erroneously trigger the decision circuits.
• the receiver 10 includes a clock recovery circuit 38 that includes a phase lock loop that locks onto the tone from the electrical data signal.
• the clock recovery circuit 38 receives a portion of the electrical signal from the RF coupler 20 and generates a clock signal having a frequency that is harmonically related to the single channel bit rate and that is synchronized or locked to the received optical data signal.
• the receiver 10 includes a first 32 and a second decision circuit 34.
• the output of the first 28 and the second filter 30 is electrically coupled to a data input 36 of the first 32 and the second decision circuit 34.
• the output of the clock recovery circuit 38 is electrically coupled to the clock input 40 of the first 32 and the second decision circuit 34.
• the first 32 and the second decision circuit 34 includes a data output 42 that generates a demultiplexed data stream having a data rate that is one- half the data rate of the received optical data signal, one embodiment, at least one of the first 32 and the second decision circuit 34 includes a complementary data output 44 that generates a complementary demultiplexed data stream that has a data rate that is one-half the data rate of the received optical data signal.
• the first 32 and the second decision circuit 34 may be any type of decision circuit. There are numerous commercially available decision circuits.
• the decision circuits 32, 34 remove amplitude and phase noise and generally clean the output data and the complementary output data.
• the decision circuits 32, 34 include a D flip/flop.
• the decision circuits 32, 34 may also include a wide-band data amplifier that improves sensitivity.
• Commercially available decision circuits according to the present invention having specified maximum data rate that are less than the data rate of the electrical data signal have been shown to operate according to the present invention.
• a first phase shifter 46 is electrically coupled between the clock recovery circuit 38 and the clock input 40 of the first decision circuit 32.
• a second phase shifter 48 is electrically coupled between the output of the first phase shifter 46 and the clock input 40 to the second decision circuit 34.
• the first phase shifter 46 modifies the phase of the clock signal to select the desired demultiplexed data stream and complementary demultiplexed data stream generated by the first decision circuit 32.
• the second phase shifter 48 modifies the phase of the clock signal to select the desired demultiplexed data stream and complementary demultiplexed data stream generated by the second decision circuit 34.
• the clock recovery circuit 38 includes a phase shifter.
• a feedback circuit 50 is electrically coupled between a control input 52 of the first phase shifter 46 and the data output 42 of the first decision circuit 32.
• the feedback circuit 50 samples a portion of the data output from the first decision circuit 32 and generates a feedback signal that instructs the phase shifter 46 to select the desired demultiplexed data stream and complementary demultiplexed data stream.
• the feedback circuit 50 may generate a feedback signal that instructs the phase shifter 46 to reduce the bit error rate.
• the feedback circuit 50 is electrically coupled between the control input 52 of the first phase shifter 46 and the complementary data output 44 of the first decision circuit 32.
• a feedback circuit 54 is electrically coupled between a control input 56 of the second phase shifter 48 and the data output 42 of the second decision circuit 34.
• the feedback circuit 54 samples a portion of the data output from the second decision circuit 34 and generates a feedback signal that instructs the phase shifter 48 to select the desired demultiplexed data stream and complementary demultiplexed data stream, h addition, the feedback circuit 54 may generate a feedback signal that instructs the phase shifter 48 to lower the bit error rate.
• the feedback circuit 54 is electrically coupled between the control input 56 of the second phase shifter 48 and the complementary data output 44 of the second decision circuit 34.
• error co ⁇ ection circuits 58 are electrically coupled to the data output 42 of the first 32 and second decision circuit 34.
• the error correction circuit 58 detects and co ⁇ ects errors in the demultiplexed signal.
• the error co ⁇ ection circuit 58 may be a forward error correction (FEC) circuit.
• FEC forward error correction
• E ⁇ or correction circuits 58 may also be electrically connected to the complementary data output 44 of the first 32 and second decision circuit 34.
• e ⁇ or detection circuits are used and an e ⁇ or signal if feedback to the transmitter.
• the operation of the optical receiver 10 can be further explained with an example of demultiplexing a 20GB/sec TMD data signal, such as a RZ data signal.
• a 20GB/sec TMD data signal such as a RZ data signal.
• the type of data signal and data rates presented in the example are given only for purposes of illustrating the invention and do not limit the invention in any way.
• the optical receiver 10 demultiplexes a 20GB/sec TMD data signal into two lOGB/sec data channels.
• the photodiode 12 detects the 20GB/sec RZ data stream and converts it into a 20GB/sec electrical data signal.
• the photodiode 12 has a bandwidth that is sufficient to detect useful data in a 20GHz signal.
• the 20 GB/sec electrical data signal is amplified by the amplifier 18, which has a bandwidth great enough to amplify the useful data.
• a 10GHz clock is recovered using the clock recovery circuit 38.
• the phase lock loop locks onto the 20GHz tone from the electrical data signal, h one embodiment, the clock recovery circuit 38 includes a 10GHz dielectric resonant oscillator and a harmonic phase detector that is configured in a feedback loop, as described in connection with the clock recovery circuit 100 of Fig. 2.
• the recovered clock signal is split and transmitted to the clock input 40 of the first 32 and the second decision circuit 34 with the appropriate phase, so that every other data bit from the 20GB/sec data stream is clocked out of the Q data port of the decision circuits 32, 34.
• the data is demultiplexed from a single 20GB/sec data stream to two lOGB/sec data streams.
• Decision circuits having maximum data rates that are significantly less than the data rate of the RZ data signal can be used for performing substantially e ⁇ or-free demultiplexing.
• Fig. 2 illustrates a clock recovery circuit 100 according to the present invention.
• the clock recovery circuit 100 includes a narrow-band amplifier 102 that amplifies the electrical data signal, i addition, the clock recovery circuit 100 includes a Phase Lock Loop (PLL) 104.
• the PLL 104 synchronizes or locks the frequency and phase of a local oscillator onto the frequency and phase of data on a single TDM channel.
• the PLL 104 is a linear PLL.
• the PLL includes a Phase Detector (PD) 106 or phase comparator, a Loop Filter (LF) 108, and a Voltage Controlled Oscillator (NCO) or Dielectric Resonant Oscillator (DRO) 110.
• PD Phase Detector
• LF Loop Filter
• DRO Dielectric Resonant Oscillator
• the PLL 104 includes a phase detector 106 that has a first input 112 that receives the filtered electrical data signal and a second input 114 that receives a signal from the NCO 110.
• the phase detector 106 compares the phase of the electrical data signal with the phase of the signal generated by the NCO or DRO 110 and generates at an output 116 a signal that includes a DC component and a superimposed AC component.
• the DC component is proportional to the phase e ⁇ or between the electrical data signal and the signal generated by the NCO or DRO 110.
• the phase detector 106 is a harmonic mixer.
• a harmonic mixer is a three-port device that includes a nonlinear element.
• the harmonic mixer mixes the electrical data signal with a local oscillator signal and generates an e ⁇ or signal that has a DC component and a superimposed AC component.
• the DC component of the e ⁇ or signal has a magnitude that is proportional to the phase e ⁇ or.
• the PLL 104 includes a loop filter 108 that has an input 118 that is electrically connected to the output 116 of the phase detector 106.
• the loop filter 108 filters the e ⁇ or signal generated by the phase detector 106 and passes the filter signal to an output 120.
• the loop filter 108 is a low pass lead-lag loop filter that includes a phase leading and phase lagging filter network. The phase leading network controls the dampening of the PLL 104.
• the loop filter 108 may be an active filter that has gain greater than one. In this embodiment, the loop filter 108 substantially cancels the AC component of the signal generated by the phase detector 106.
• the NCO 110 has a control input 122 that is electrically connected to the output 120 of the loop filter 108.
• the NCO 110 generates a local oscillator signal that has a frequency, which is determined by the magnitude of the e ⁇ or signal.
• the NCO 110 is a Dielectric Resonator Oscillator (DRO).
• the clock recovery circuit 100 includes a Current Controlled Oscillator (CCO).
• the phase e ⁇ or between the output signal of the NCO or DRO and the reference signal is substantially zero or a constant. If a phase e ⁇ or accumulates, the PLL 104 changes the frequency and/or phase of the oscillator so that the phase error is reduced to a minimum, thereby synchronizing or locking the phase of the output signal to the phase of the reference signal.
• the demultiplexer and receiver of the present invention can be used with electronic communication systems as well as optical communication systems.
• the invention was described in connection with demultiplexing TDM data signals, the methods and apparatus of the present invention can be used to demultiplex numerous other types of high data rate signals.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Quality & Reliability (AREA)
• Time-Division Multiplex Systems (AREA)
• Optical Communication System (AREA)

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• 2001
  • 2001-12-12 EP EP01988323A patent/EP1344340A2/de not_active Withdrawn
  • 2001-12-12 WO PCT/US2001/048696 patent/WO2002049248A2/en not_active Ceased
  • 2001-12-12 AU AU2002241640A patent/AU2002241640A1/en not_active Abandoned

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