Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/14—Error detection or correction of the data by redundancy in operations
  • G06F11/1402—Saving, restoring, recovering or retrying
  • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
  • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
  • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Definitions

• the present invention relates to digital circuits protected against the effects of disturbances such as transient disturbances resulting from external causes or time faults related to the manufacture of the circuits.
• a transient fault is produced by a localized disturbance originating for example from particle bombardments.
• the capacities of the nodes and the supply voltages of modern integrated circuits are increasingly low, the charges present on the nodes become very low. Thus, these circuits become sensitive to increasingly weak disturbances.
• the logical value of a node can be reversed by particles with very low energies. In past technologies of integrated circuits, it was mainly the particles hitting the memory points which produced logical faults.
• a time fault results from the fact that, while a circuit element is normally designed to have a certain reaction time, this time, as a result of a localized manufacturing defect, may be greater than what was expected by the designer. Thus, if sampling is carried out after the normal reaction time of the circuit, this sampling can occur when the circuit has not yet switched. Due to the increase in density and speed of operation of modern integrated circuits, such faults are becoming more common and very difficult to test by the usual test programs and can therefore remain in a normally tested circuit. .
• temporary fault or simply fault, a fault resulting from a transient disturbance or a manufacturing defect modifying the response time of a circuit element.
• an object of the present invention is to simplify the problems of protecting a logic circuit against disturbances.
• the present invention is essentially based on an analysis of the operation of the various elements of a system and proposes to adopt for the various parts of a system specific treatments for protection against errors or for repairing errors. .
• the solution at minimum cost will thus be chosen for each block.
• a detection and recovery mechanism will be used, making it possible to correct the errors produced by a transient fault by repeating a small number of the most recent.
• recovery mechanisms are provided operating on a small number of operating cycles.
• a recovery will correct the errors produced by a transient fault.
• an error detection technique accompanied by a recovery operating on the last k operating cycles.
• a detection and recovery will not correct errors due to a transient fault. Indeed, an error produced by such a circuit could induce an addressing error during a write operation and destroy data stored at this address for more than k operating cycles.
• Another fault with a similar consequence is a fault which triggers a write during a read cycle or during a cycle of non-access to the memory.
• Combinatorial circuits concerned by this solution are, for example, a combinatorial part generating memory addresses or generating write / read signals, address decoders, etc.
• An error on the write / read signal will have two polarities: error of the type reading at the place of writing (1 instead of 0 on R / W) or of the type writing at the place of reading (0 instead of 1 on R / W).
• the second polarity is dangerous and must be avoided, while it will be enough to detect the first and trigger a recovery to correct the errors produced.
• the integration of the MPE mechanisms inside the circuit occupies only a small storage space to save the states necessary for the recovery, the backup can be carried out continuously, and short-term recoveries can be provided.
• the present invention also provides various embodiments of fault immunization or error avoidance mechanisms suitable, for example, for circuits controlling long-term memories.
• the present invention more particularly provides a digital circuit architecture comprising combinational circuits, short-term memory circuits not capable of storing data for more than k operating cycles, long-term memory circuits capable of to store data for more than k operating cycles of the circuit, comprising separate interference protection systems for the different types of circuits and according to the functionality of these circuits: a) for long-term storage circuits, means of fault immunization; b) for short-term storage circuits, error detection and recovery mechanisms are used; c) for combinational circuits controlling short-term memories and / or determining only data to be written in long-term memories, error detection and recovery systems are used in the memories concerned.
• some of the combinational circuits capable of providing control instructions to long-term memories are protected by an avoidance mechanism for errors of polarity, and possibly a mechanism for detecting opposite polarity errors.
• FIG. 1 represents the structure general of a complex digital circuit
• FIGS. 2 to 12 illustrate only by way of example various embodiments of error avoidance mechanisms according to the present invention.
• a complex digital circuit is divided into various blocks which are grouped logically according to their functionalities and their associations with memories. There are four main groups of elements in a complex digital circuit. Each group corresponds to one or more integrated circuits or to one or more parts of integrated circuits.
• a first group 10 comprises combinational circuits which are either pure combinational circuits which do not act specifically on memories, or else combinative circuits capable of acting on short-term memories or other memory elements (latch) in which it is not possible to find data stored for more than k operating cycles, or alternatively combinational circuits supplying data (data) and not command signals (control) to long-term storage elements.
• a second group 11 comprises short-term storage elements which are not capable of containing data stored for more than k operating cycles.
• a third group 12 includes combinational circuits capable of supplying control signals to memories capable of storing data during more than k operating cycles.
• a fourth group 13 includes long-term storage elements capable of storing data for more than k operating cycles.
• an error detection and recovery process may be used.
• one or more state preservation mechanisms 20 save data entering or leaving the storage parts during the last k operating cycles.
• the value of k will be chosen by the designer who will thus make a selection of the storage elements 11 and of the storage elements 13 taking takes into account the reaction time of the system following an occurrence of a fault, so as to be sure that, after the detection of errors, it can generate an interruption in a duration shorter than the duration of the number of stored operations.
• this detection and recovery system is the least bulky and least expensive system on the surface in a circuit.
• the long-term memories will also be associated with a state preservation mechanism saving data among the data of the last k cycles to allow recovery in the event of detection of errors in a combinatorial element recording data in such memories.
• Various error detection circuits are known in the prior art, in particular as set out by the present inventor in the above referenced patent application.
• the combinatorial parts 12 capable of supplying control signals (addressing, reading / writing, etc.) to long-term memories and these long-term memories 13 the technique described above for detecting errors and recovery will generally be ineffective as old data may be irretrievably lost. We will therefore provide circuits immune to faults intrinsically or logically.
• certain errors can be repaired by error detection and recovery type techniques, in particular addressing or reading / writing errors of a certain polarity.
• the SRAM and DRAM memory blocks used in electronic circuits are most often memories that can store information for a long time and correspond to the fourth group.
• the flip-flops of a circuit are generally, as mentioned above, short-term memories
• flip-flops which renew their content at each clock pulse.
• some flip-flops can be fitted with a hold status command, such that the content of the flip-flop is unchanged as long as the hold command is activated.
• the flip-flop then becomes, during the activation of the hold command, a long-term memory and will be treated as an element of the fourth group.
• a fault immunization mode is then to duplicate the scale and, when an error on the scale is detected and the hold signal is activated, to use the duplicated scale to restore the contents of the scale.
• the flip-flop control signals can be protected by means of fault immunization.
• the present invention also proposes various embodiments of fault immunization or error avoidance circuits which will be described in relation to FIGS. 2 to 12.
• an error avoidance mechanism of a polarity for a combinational logic circuit 30 having at least one output comprises a circuit for generating an error control code 40 for said output, and an element forcing state 44 disposed at said output, controlled by the control code generation circuit 40 to be transparent when the control code is correct, and to force said output to a predetermined state, corresponding to a polarity d error opposite to the error polarity which the circuit must avoid, when the control code is incorrect.
• the error control code generation circuit of the error avoidance mechanism generates an error detection output which takes the value 1 (0) to indicate the occurrence of d 'an error and the value 0 (1) to indicate correct operation
• said state forcing element is an OR gate (AND) having one of its inputs connected to the output of the combinational logic circuit and the other of its inputs connected to the error detection output of the error control code generation circuit 40, so that when the output of the error control code generation circuit indicates the occurrence of an error , the output of the forcing element state takes the value 1 (0) corresponding to said predetermined state, and when the output of the error control code generation circuit indicates correct operation, the output of the state forcing element takes the same value as the output of the combinational logic circuit.
• an error control code generation circuit of the error avoidance mechanism for a combinational logic circuit 30 includes a code prediction circuit 45 which calculates an error detecting code (such as a bit parity) for the outputs of the combinatorial circuit from signals other than the output of the combinatorial circuit, a code calculation circuit 47 which calculates the error detector code from the outputs of the combinatorial circuit, and a verification circuit 42 the error detector code generated by the prediction circuit and the error detector code generated by the calculation circuit.
• an error detecting code such as a bit parity
• an error detection signal is obtained at the output of circuit 42.
• This signal is described here in the context of an error avoidance process . This signal could also be used to command a restart.
• the circuit for generating the error control code of the error avoidance mechanism for a combinational logic circuit 30, comprises a duplicate combinational logic circuit 30 ', the state forcing element 44 being provided for be transparent when the outputs of the combinational logic circuit and of the duplicate combinational logic circuit are identical, and, when these outputs are distinct, produce at its output a predetermined state.
• the state forcing element is an OR gate (AND) so that, in the absence of error, the output of the state forcing element takes the same value as the outputs of the combinational circuit.
• the state forcing element 44 of the error avoidance mechanism for a combined logic circuit roof 30 comprises an initialization device 52 which systematically and beforehand puts the output of the state forcing element into said predetermined state, and a modification device 53, which subsequently modifies the value of this output only if the control code supplied by the error control code generation circuit 40 is correct and that said predetermined state is different from the value supplied at the output of the combinational logic circuit.
• the error control code circuit comprises a duplicate combinational logic circuit
• said state forcing element is composed of an initialization device putting the output before and systematically the state forcing circuit in the so-called predetermined state, and a modification device which subsequently modifies the value of the output, only if the corresponding outputs of the combinational logic circuit and of the duplicated logic circuit have identical values and said predetermined state is different from the state corresponding to the output values of the combinational logic circuit.
• the circuit for generating the error control code of the error avoidance mechanism for a combinational logic circuit 30, comprises a duplicate combinational logic circuit 30 '.
• the modification device 53 is composed of two transistors interconnected in series which connect the output of the state forcing circuit to the voltage Vdd (Gnd) and which are respectively controlled by the output of the combinational logic circuit 30 and by the output of the circuit 30 'duplicated combinatorial logic.
• the initialization device 52 is composed of a switch which connects the output to the voltage Gnd (Vdd) when a control signal Cl is active, the control signal being activated during a period of the operating cycle called the phase of initialization.
• a switch 56 is used to disconnect the output of the state forcing circuit of the output of the modification circuit when the control signal C1 is active.
• the circuit for generating the error control code of the error avoidance mechanism for a combinative logic circuit 30, comprises a delay element 50 which delays the output of the combinative logic circuit by a predetermined duration ⁇ greater the maximum duration of transient errors.
• the state forcing element 44 is designed to be transparent when the outputs of the combinational logic circuit and of the delay element are identical, and to produce at its output a predetermined state, when these outputs are distinct.
• the error avoidance mechanism for a combinational logic circuit 30 is combined with an error detection circuit 61 making it possible to initiate a resumption of the most recent operations.
• the error detection circuit can be implemented by a comparator which signals an error when the outputs of the combinational logic circuit 30 and the delay element 50 are distinct during a part of the operating cycle the duration of which is greater than a certain threshold.
• the error detection circuit can be produced by a comparator 61 which signals an error when the outputs of the Combinatorial logic circuit and the duplicate combinatorial logic circuit are distinct during a period of the operating cycle whose duration is greater than a certain threshold.
• a memory decoder generates a plurality of outputs, only one of which takes the value 1 at each cycle of the memory operation.
• the decoder can be protected by an error avoidance circuit to prevent a type 1 error instead of 0 (polarity error 1) occurs on an output of the decoder, which would lead to the selection of a memory word which should not be selected.
• a type 1 error avoidance circuit instead of 0 will ensure that this error cannot occur. It is not necessary, especially if the decoder has a very large number of outputs, to correct type 0 errors instead of 1. However, provision may be made to detect them to activate a recovery cycle. This last type of error leads to the situation where all the outputs of the decoder are equal to 0. To detect these errors, it is possible to use a circuit which signals erroneous operation when a number of outputs of the decoder other than 1 takes the value 1. This circuit makes it possible to detect errors of both types on the outputs of the decoder. A simpler circuit making it possible to detect only errors of type 0 instead of 1 (which are the errors which interest us here) consists of a logic OR gate.
• the combinational logic circuit 30 provides a plurality of the outputs protected by a plurality of state forcing elements 44.
• Said predetermined state is 0
• the error detection circuit is an OR (AND) logic gate 61 which signals
• the error avoidance mechanism comprises a delay element 50 of a predetermined duration greater than the maximum duration of the transient errors, and a state forcing element 44, the circuit also comprises a circuit bypass (mux) 70, making it possible to bypass the delay element when a control signal C2 is active.
• the state forcing element is intended to be transparent when the outputs of the combinational logic circuit and of the delay element are identical, and to produce at its output a predetermined value when said outputs are distinct.
• the error avoidance mechanism comprises a delay element 50 of a predetermined duration greater than the maximum duration of the transient errors, a bypass circuit 70 making it possible to force the output of the delay element to the value 1 when a control signal C2 is equal to 1, and a state forcing element 44 produced by an AND gate having an input connected to the output of the combinational logic circuit 30 and another input connected to the output of the circuit 70.
• the error avoidance mechanism comprises a delay element 50, and a state forcing element 44.
• the circuit also includes a bypass circuit 70 making it possible to bypass the state forcing element when 'a C2 control signal is active.
• the state forcing element is intended to be transparent when the outputs of the combinational logic circuit and of the delay element are identical, and to produce at its output a predetermined value when said outputs are distinct.
• the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. In particular, account may be taken of various specific cases in which it will be possible to use a detection and recovery mechanism rather than providing elements intrinsically immune to faults.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Quality & Reliability (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Detection And Correction Of Errors (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Semiconductor Integrated Circuits (AREA)
• Logic Circuits (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=8868280

Family Applications (1)

Country Status (4)

Families Citing this family (2)

Family Cites Families (13)

• 2001
  • 2001-10-12 FR FR0113241A patent/FR2830972B1/fr not_active Expired - Fee Related
• 2002
  • 2002-10-11 US US10/492,294 patent/US20040255204A1/en not_active Abandoned
  • 2002-10-11 EP EP02785543A patent/EP1451688A2/de not_active Withdrawn
  • 2002-10-11 WO PCT/FR2002/003484 patent/WO2003032160A2/fr not_active Ceased
• 2007
  • 2007-09-27 US US11/904,762 patent/US20080028278A1/en not_active Abandoned

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events