EP1489623A1 - Dispositif de mémoire multibit et méthodes de programmation et de lecture du même - Google Patents

Dispositif de mémoire multibit et méthodes de programmation et de lecture du même Download PDF

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Publication number
EP1489623A1
EP1489623A1 EP03026610A EP03026610A EP1489623A1 EP 1489623 A1 EP1489623 A1 EP 1489623A1 EP 03026610 A EP03026610 A EP 03026610A EP 03026610 A EP03026610 A EP 03026610A EP 1489623 A1 EP1489623 A1 EP 1489623A1
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EP
European Patent Office
Prior art keywords
multilevel memory
voltage
memory device
current
core
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Granted
Application number
EP03026610A
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German (de)
English (en)
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EP1489623B1 (fr
Inventor
Yi-Chou Chen
Chih-Yuan Lu
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Macronix International Co Ltd
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Macronix International Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

Definitions

  • the present invention relates generally to memory devices and, more particularly, to a method of programming a threshold changing material of a memory cell to allow for multilevel data storage and associated reading techniques.
  • FIG. 1 is a graph illustrating a plot of the resistance versus the current for a multi-level chalcogenide random access memory (RAM). As is illustrated by line 102, the resistance steps up according to each current increment.
  • the resistance of chalcogenide may be tuned, however, one of the shortcomings associated with defining the stages through the resistance is that the resistance difference is difficult to sense because the sensing margin is small for multi-level applications and the sensing time for the high resistance stage will be long.
  • the current to read a cell is usually 20 ⁇ A. If we apply 0.1 V on a cell, and the cell resistance may be 5k, 50k, 500k and 5M, the current read will be 20 ⁇ A, 2 ⁇ A, 0.2 ⁇ A (which can be hardly sensed), and 20 nA (the same order as noise), respectively. That is, it is almost impossible to sense all the states at that level.
  • the present invention provides a memory cell structure that is capable of defining multiple bits per cell through the use of a threshold changing material.
  • a multilevel memory core includes a word line and a bit line.
  • a core cell in electrical communication with the word line and the bit line is also included.
  • the core cell includes a threshold changing material.
  • the threshold changing material is programmed to define multiple levels for storage where each of the multiple levels for storage is associated with a corresponding threshold voltage.
  • the threshold changing material is programmed by applying different energy pulses to the threshold changing material.
  • the voltage threshold is tuned through the application of the different energy pulses.
  • a method for reading a multilevel memory device includes applying a read voltage to the multilevel memory device. Then, a state of a current associated with the read voltage is determined. Next, an access state of the multilevel memory device based on the current is determined.
  • the multilevel memory device is programmed prior to being read.
  • the programming includes tuning a voltage threshold through the application of varying energy pulses.
  • a method for reading multiple levels of a multilevel memory device begins with applying a voltage to a threshold changing material of the multilevel memory device. Then, a current related to the voltage is sensed to distinguish between each of the multiple levels.
  • the method of reading the multilevel memory device of the present invention may be applied in numerous memory/solid state device applications.
  • One of the significant advantages of the read method is the speed and the sensing margin achieved when reading the current as opposed to sensing resistance.
  • a threshold voltage associated with a threshold changing material is obtained by applying different energy pulses in order to define different threshold voltages.
  • the threshold changing material is a chalcogenide material.
  • V th threshold voltage
  • the threshold voltage, V th of a material capable of changing V th is discussed in related U.S. Patent Application No. (Attorney Docket No. MXICP020), filed on even date herewith, and entitled " Method for Adjusting the Threshold Voltage for a Memory Cell.”. The disclosure of this related application is incorporated herein by reference for all purposes.
  • the threshold voltage the current associated with each stage is distinguishable. Consequently, by sensing the current, the corresponding states may be determined. Therefore, within one memory core cell multiple states may exist and the different states correspond to a sensed current.
  • FIG. 2 is a simplified schematic diagram of a portion of a typical chalcogenide memory array.
  • Memory array portion 112 includes word lines 108 a and 108b, bit lines 110a and 110b, transistor device 104, and chalcogenide device 106.
  • Transistor device 104 functions as a steering device, i.e., an access transistor, which provides access to chalcogenide device 106 from the corresponding word line and bit line.
  • transistor device 104 may by an access P-N diode, a bipolar junction transistor (BJT), or other suitable transistor.
  • BJT bipolar junction transistor
  • chalcogenide device 106 functions as a memory device.
  • Figure 3 is a normalized current (I)-normalized voltage (V) curve where different programming pulses were applied to applied to a threshold changing material in order to define different threshold voltages.
  • the V th of chalcogenide may be adjusted by applying energy into the film. Therefore, there may be different V th within a single memory core cell.
  • the steering transistor of the selected cell may be activated and a certain energy pulse is applied to the cell. The energy pulse is associated with a certain duration and profile. For example, to program a cell a voltage from 0.1 V to 20 V may be applied.
  • the duration may be 1 nanosecond (ns) to 1000 ns.
  • V th The various states illustrated in Figure 3 are associated with the four threshold voltages (V th ). That is, V th1 is associated with a first state, V th2 is associated with a second state, V th3 is associated with a third state, and V th4 is associated with a fourth state.
  • Table 1 below provides a truth table associated with the four states illustrated in Figure 3.
  • state 1 is defined when the read voltage V a is between V th1 and V th2 .
  • States 1 and 2 are defined when the read voltage V b is between V th2 and V th3 .
  • States 1, 2, and 3 are defined when the read voltage V c is between V th3 and V th4 .
  • States 1, 2, 3, and 4 are defined when the read voltage V d is greater than V th4 .
  • Figure 4 is a flow chart diagram illustrating the method operations for reading the multi-level states associated with a threshold changing material.
  • the method initiates with decision operation 122 where a current is measured at read voltage V b . If the current is high (on), then the method advances to operation 124 where the state is either state one or state two. The method then moves to decision operation 126 where the current is measured at read voltage V a . If the current is high (on), then the associated state is state one as indicated in box 128. If the current measured in decision operation 126 is low (off), then this is an indication of state two 130. Returning to decision operation 122, if the current measured at V b is low (off), then this is an indication of either state three or four as represented by box 132.
  • the method then proceeds to decision operation 134 where the current is measured at voltage V c . If the current measured at V c is high (on), then this is an indication of state three 136. If the current measured at V c is low (off), then the associated state here is state four as represented by box 138.
  • Figure 5 is a flowchart diagram of an alternative method for reading the multi-level states of a threshold changing material described with reference to Figure 4.
  • the method initiates with a decision operation 140 where a current is measured at voltage V a . If the current associated with read voltage V a indicates high (on), then the method proceeds to operation 142 which indicates that the state is either state two, three or four. The method then proceeds to decision operation 144 where the current is measured at read voltage V b . If the current associated with V b is high (on), this indicates either state three or state four in box 146. The method then moves to decision operation 148 where the current is measured at voltage V c . If the voltage at V c is high (on), then state three is indicated as provided by box 150.
  • a multi-level chalcogenide memory is described herein.
  • the multi-level data are stored according to different threshold voltages.
  • the threshold voltage is tuned by applying different energy pulses (further information on applying different energy pulses to tune the threshold voltage has been incorporated herein by reference).
  • two reading methods have been discussed. It should be appreciated in each of the reading methods the reading voltage should be higher than the threshold voltage. Accordingly, by changing the threshold voltage of the threshold changing material, a multi-level memory is provided.
  • a multi-level non-volatile random access memory may be achieved in one embodiment of the invention. Since the reading sensing margin is very large ,as opposed to a resistance-based model, the multi-level stages may be easily discerned. Reading the current suffices to provide a distinguishing feature. Furthermore, the reading speed is relatively fast as compared to other reading speeds, i.e., the speed associated with reading resistance.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
EP03026610A 2003-06-18 2003-11-19 Dispositif de mémoire multibit et méthodes de programmation et de lecture du même Expired - Lifetime EP1489623B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/465,012 US7180767B2 (en) 2003-06-18 2003-06-18 Multi-level memory device and methods for programming and reading the same
US465012 2003-06-18

Publications (2)

Publication Number Publication Date
EP1489623A1 true EP1489623A1 (fr) 2004-12-22
EP1489623B1 EP1489623B1 (fr) 2008-10-15

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Country Status (6)

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US (1) US7180767B2 (fr)
EP (1) EP1489623B1 (fr)
JP (1) JP5611499B2 (fr)
CN (1) CN100578668C (fr)
DE (1) DE60324117D1 (fr)
TW (1) TWI223258B (fr)

Cited By (6)

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WO2005017907A3 (fr) * 2003-08-04 2005-06-02 Intel Corp Mecanisme de polarisation de lecture pour memoires a changement de phase
WO2006035326A1 (fr) * 2004-09-30 2006-04-06 Koninklijke Philips Electronics N.V. Circuit integre pourvu de cellules de memoires comprenant une resistance programmable et procede d'adressage de cellules de memoire comprenant une resistance programmable
EP1881540A3 (fr) * 2006-07-18 2009-01-21 Qimonda North America Corp. Cellule mémoire à changement de phase dotée d'une caractéristique de programmation en escalier
EP1881541A3 (fr) * 2006-07-18 2009-04-08 Qimonda North America Corp. Cellule mémoire à changement de phase dotée d'une caractéristique de programmation en escalier
EP1881539A3 (fr) * 2006-07-18 2009-05-06 Qimonda North America Corp. Cellule mémoire à changement de phase avec une caractéristique de programmation en gradins
WO2010097302A1 (fr) 2009-02-24 2010-09-02 International Business Machines Corporation Procédé de lecture de mémoire tenant compte des effets de dérive de résistance

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US7138687B2 (en) * 2004-01-26 2006-11-21 Macronix International Co., Ltd. Thin film phase-change memory
US8116159B2 (en) 2005-03-30 2012-02-14 Ovonyx, Inc. Using a bit specific reference level to read a resistive memory
KR100684908B1 (ko) * 2006-01-09 2007-02-22 삼성전자주식회사 다수 저항 상태를 갖는 저항 메모리 요소, 저항 메모리 셀및 그 동작 방법 그리고 상기 저항 메모리 요소를 적용한데이터 처리 시스템
US20070267620A1 (en) * 2006-05-18 2007-11-22 Thomas Happ Memory cell including doped phase change material
KR100887069B1 (ko) * 2007-07-24 2009-03-04 주식회사 하이닉스반도체 상 변화 메모리 장치
US7881100B2 (en) * 2008-04-08 2011-02-01 Micron Technology, Inc. State machine sensing of memory cells
US20100090189A1 (en) * 2008-09-15 2010-04-15 Savransky Semyon D Nanoscale electrical device
US7885101B2 (en) * 2008-12-29 2011-02-08 Numonyx B.V. Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory
KR101057725B1 (ko) * 2008-12-31 2011-08-18 주식회사 하이닉스반도체 멀티 레벨 셀 데이터 센싱 장치 및 그 방법
US8605495B2 (en) 2011-05-09 2013-12-10 Macronix International Co., Ltd. Isolation device free memory
US9281061B2 (en) 2012-09-19 2016-03-08 Micron Technology, Inc. Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit
KR102157357B1 (ko) * 2014-06-16 2020-09-17 삼성전자 주식회사 메모리 장치 및 상기 메모리 장치의 독출 방법
JP2016033843A (ja) * 2014-07-31 2016-03-10 株式会社東芝 不揮発性記憶装置およびその駆動方法
US10134470B2 (en) 2015-11-04 2018-11-20 Micron Technology, Inc. Apparatuses and methods including memory and operation of same
US9978810B2 (en) 2015-11-04 2018-05-22 Micron Technology, Inc. Three-dimensional memory apparatuses and methods of use
US10446226B2 (en) * 2016-08-08 2019-10-15 Micron Technology, Inc. Apparatuses including multi-level memory cells and methods of operation of same
US10381075B2 (en) 2017-12-14 2019-08-13 Micron Technology, Inc. Techniques to access a self-selecting memory device
US10546632B2 (en) * 2017-12-14 2020-01-28 Micron Technology, Inc. Multi-level self-selecting memory device
US11302390B2 (en) * 2020-07-10 2022-04-12 Micron Technology, Inc. Reading a multi-level memory cell
FR3148862B1 (fr) * 2023-05-19 2025-10-17 St Microelectronics Int Nv Lecture d’un dispositif de mémoire non volatile multi-niveaux, en particulier à changement de phase, et dispositif de mémoire non volatile multi-niveaux

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Cited By (8)

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Publication number Priority date Publication date Assignee Title
WO2005017907A3 (fr) * 2003-08-04 2005-06-02 Intel Corp Mecanisme de polarisation de lecture pour memoires a changement de phase
US7308067B2 (en) 2003-08-04 2007-12-11 Intel Corporation Read bias scheme for phase change memories
WO2006035326A1 (fr) * 2004-09-30 2006-04-06 Koninklijke Philips Electronics N.V. Circuit integre pourvu de cellules de memoires comprenant une resistance programmable et procede d'adressage de cellules de memoire comprenant une resistance programmable
US8335103B2 (en) 2004-09-30 2012-12-18 Nxp B.V. Integrated circuit with memory cells comprising a programmable resistor and method for addressing memory cells comprising a programmable resistor
EP1881540A3 (fr) * 2006-07-18 2009-01-21 Qimonda North America Corp. Cellule mémoire à changement de phase dotée d'une caractéristique de programmation en escalier
EP1881541A3 (fr) * 2006-07-18 2009-04-08 Qimonda North America Corp. Cellule mémoire à changement de phase dotée d'une caractéristique de programmation en escalier
EP1881539A3 (fr) * 2006-07-18 2009-05-06 Qimonda North America Corp. Cellule mémoire à changement de phase avec une caractéristique de programmation en gradins
WO2010097302A1 (fr) 2009-02-24 2010-09-02 International Business Machines Corporation Procédé de lecture de mémoire tenant compte des effets de dérive de résistance

Also Published As

Publication number Publication date
TWI223258B (en) 2004-11-01
EP1489623B1 (fr) 2008-10-15
US20040257854A1 (en) 2004-12-23
JP2005012186A (ja) 2005-01-13
CN1574091A (zh) 2005-02-02
TW200501160A (en) 2005-01-01
CN100578668C (zh) 2010-01-06
DE60324117D1 (de) 2008-11-27
JP5611499B2 (ja) 2014-10-22
US7180767B2 (en) 2007-02-20

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