EP1494198A2 - Verfahren zum Steuern einer Anzeigetafel - Google Patents

Verfahren zum Steuern einer Anzeigetafel Download PDF

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Publication number
EP1494198A2
EP1494198A2 EP04014739A EP04014739A EP1494198A2 EP 1494198 A2 EP1494198 A2 EP 1494198A2 EP 04014739 A EP04014739 A EP 04014739A EP 04014739 A EP04014739 A EP 04014739A EP 1494198 A2 EP1494198 A2 EP 1494198A2
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EP
European Patent Office
Prior art keywords
display
subfields
address
display line
light emission
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Withdrawn
Application number
EP04014739A
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English (en)
French (fr)
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EP1494198A3 (de
Inventor
Hirofumi Pioneer Corporation Honda
Tetsuro Pioneer Corporation Nagakubo
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Pioneer Corp
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Pioneer Corp
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Publication of EP1494198A2 publication Critical patent/EP1494198A2/de
Publication of EP1494198A3 publication Critical patent/EP1494198A3/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/2803—Display of gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G09G3/2935—Addressed by erasing selected cells that are in an ON state
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/204—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames being organized in consecutive sub-frame groups
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2044—Display of intermediate tones using dithering
    • G09G3/2051—Display of intermediate tones using dithering with use of a spatial dither pattern
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2059—Display of intermediate tones using error diffusion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods

Definitions

  • the present invention relates to a driving method for a display panel in which pixel cells serving as pixels are arranged on respective display lines.
  • the subfield method is known as a driving method for displaying an image corresponding with a video input signal on the PDP.
  • the subfield method divides a single-field display period into a plurality of subfields and causes each of the discharge cells to selectively discharge light in each subfield in accordance with the luminance level represented by the video input signal. Accordingly, an intermediate luminance corresponding with the total light emission period within the single-field period is visible (or perceived).
  • Fig. 1 of the attached drawings shows an example of a light emission drive sequence based on this subfield method.
  • This emission drive sequence is disclosed in, for example, Japanese Patent Application Kokai (Laid-Open Publication) No. 2000-227778.
  • the light emission drive sequence shown in Fig. 1 divides a single field period into 14 subfields, namely the subfields SF1 to SF14. All the discharge cells of the PDP are initialized in a lit mode only in the leading subfield SF1 of these subfields SF1 to SF14 (Rc) . Each of the subfields SF1 to SF14 sets some of the discharge cells to an unlit mode in accordance with the video input signal (Wc) and causes only the discharge cells of lit mode to discharge light over the period allocated to the subfield concerned (Ic).
  • Fig. 2 of the attached drawings shows an example of a light emission drive pattern in a single field period of each discharge cell that is driven on the basis of this light emission drive sequence (see Japanese Patent Application Kokai No. 2000-2277785).
  • the discharge cells initialized in the lit mode in the leading subfield SF1 are then set to the unlit mode in a particular one subfield of the subfields SF1 to SF14, as indicated by the black circles.
  • the discharge cell does not re-enter the lit mode until the one field period ends. Accordingly, during the period until the discharge cells are set to the unlit mode, as indicated by the white circles, the discharge cells discharge light continuously in these subfields.
  • Each of the fifteen different light emission patterns shown in Fig. 2 has a different total light emission period within a single field period, and hence fifteen different intermediate luminances are rendered. That is, an intermediate luminance display for (N+1) grayscales (N being the number of subfields) is feasible.
  • Error diffusion processing converts the video input signal into 8-bit pixel data, for example, for each pixel.
  • the upper 6 bits of the pixel data is treated as display data and the remaining lower two bits of the pixel data is treated as error data.
  • the error data of the pixel data are weighted and added based on the respective peripheral pixels and the resultant is reflected in the display data.
  • a pseudo-representation of the luminance of the lower two bits of the original pixel is provided by the peripheral pixels, and, consequently, a luminance grayscale representation of the 8 bits of pixel data is possible by means of the six bits of display data.
  • dither processing is performed on the six-bit error-diffusion-processed pixel data obtained by the error diffusion processing.
  • a single pixel unit is rendered from a plurality of adjoining pixels, and dither coefficients consisting of different coefficient values are allocated and added to the error-diffusion-processed pixel data corresponding with the respective pixels in the single pixel unit.
  • the luminance of the 8-bit original data can be represented by only the upper four bits of the dither-added pixel data. Therefore, the upper four bits of the dither-added pixel data are extracted and allocated to each of the 15 different light emission patterns shown in Fig. 2 as multiple grayscale pixel data PDs.
  • a dither coefficient addition is performed regularly on the pixel data by means of dither processing and so forth, a pseudo pattern which is completely independent of the video input signal, i.e. a so-called dither pattern, is sometimes observed, which compromises the quality of the displayed image.
  • An object of the present invention is to provide a display panel driving method capable of creating a favorable image display in which dither patterns are suppressed.
  • an improved method of grayscale-driving a display panel in accordance with pixel data derived from a video signal includes a plurality of display lines, with a plurality of pixel cells serving as pixels being arranged on each display line.
  • a display period of a single field of the video signal is divided into a plurality of subfields.
  • the method includes dividing one of the subfields into M lower subfields. M is an integer greater than one.
  • M groups of display lines are prepared by sequentially taking every M display lines from the display lines. First to Mth address steps are performed in the M lower subfields respectively and sequentially.
  • Each address step sets the pixel cells belonging to the display lines of the display line group concerned, to a drive mode determined by the pixel data.
  • a first light emission step is performed to cause the pixel cells whose drive mode is a lit mode, to emit light directly before or after the address step concerned.
  • Another subfield is divided into N lower subfields. N is smaller than M.
  • N groups of address steps are prepared from the first to Mth address steps.
  • Each address step group includes one or more address steps, and at least one address step group includes a plurality of address steps.
  • the N address step groups are performed in the N lower subfields respectively and sequentially.
  • a second light emission step is performed to cause the pixel cells whose drive mode is the lit mode, to emit light directly before or after the address step group concerned.
  • the PDP 100 includes a front-side substrate (not shown) that functions as a display surface, and a rear-side substrate (not shown) that is disposed in a position opposite the front-side substrate.
  • a discharge space filled with discharge gas is defined between the front-side substrate and rear-side substrate.
  • Belt-shaped row electrodes X 1 to X n and row electrodes Y 1 to Y n are alternately arranged in parallel to each other and provided on the front-side substrate.
  • Belt-shaped column electrodes D 1 to D m arranged to cross over the row electrodes are provided on the rear-side substrate.
  • the row electrodes X 1 to X n and Y 1 to Y n are arranged such that the first to nth display lines of the PDP 100 are defined by n pairs of row electrodes X i and Y i .
  • Discharge cells G serving as pixels are formed at the intersection points (including the discharge space) between the row electrode pairs and column electrodes. That is, (n ⁇ m) discharge cells G (1,1) to G (n,m) are formed in a matrix shape on the PDP 100.
  • a pixel data conversion circuit 1 converts a video input signal into 6-bit pixel data PD, for example, for each pixel, and then supplies this pixel data PD to a multiple grayscale processing circuit 2.
  • the multiple grayscale processing circuit 2 includes a line dither offset value generation circuit 21, an adder 22, and a lower bit discard circuit 23.
  • the line dither offset value generation circuit 21 first generates eight line dither offset values LD with the values '0' to '7' respectively to match eight display line groups of the PDP 100.
  • the first to nth display lines of the PDP 100 are separated by eight lines and grouped as shown below:
  • N is a natural number equal to or less than (1/8) ⁇ n.
  • the line dither offset value generation circuit 21 repeatedly executes, for each field and with 8 fields forming one cycle, the alteration of allocation of the line dither offset values LD to the display line groups, as shown in Figs. 4A to 4H.
  • the line dither offset value generation circuit 21 allocates, in the very first field, the following line dither offset values LD to the eight display line groups:
  • the line dither offset values LD are allocated in the second field:
  • the line dither offset values LD are allocated in the third field:
  • the line dither offset values LD with the following values are allocated in the fourth field:
  • the line dither offset values LD are allocated in the seventh field:
  • the line dither offset values LD with the following values are allocated in the eighth field:
  • the line dither offset value generation circuit 21 provides the adder 22 with the line dither offset values LD allocated to the display lines belonging to discharge cells corresponding with pixel data PD supplied by the pixel data conversion circuit 1.
  • the adder 22 provides the lower bit discard circuit 23 with line-offset-added pixel data LF, which is prepared by adding the line dither offset values LD to pixel data PD supplied by the pixel data conversion circuit 1.
  • the lower bit discard circuit 23 discards the lower three bits of the line-offset-added pixel data LF and then supplies the remaining three upper bits of this data LF to the drive data conversion circuit 3 as multiple grayscale pixel data MD.
  • a drive data conversion circuit 3 converts multiple grayscale pixel data MD into 4-bit pixel drive data GD in accordance with a data conversion table shown in Fig. 5 and supplies the four-bit pixel drive data GD to a memory 4.
  • the memory 4 sequentially captures and stores the 4-bit pixel drive data GD. Each time the memory 4 finishes the writing of one image-frame (n rows ⁇ m columns) of pixel drive data GD 1,1 to GD n,m , the memory 4 divides the pixel drive data GD 1,1 to GD n,m into bit digits (0th to 3rd bits) and reads one display line's worth of this data at a time in correspondence with the subfields SF0 to SF3 respectively. The memory 4 supplies m pixel drive data bits corresponding to one display line to a column electrode driver circuit 5 as the pixel drive data bits DB1 to DBm.
  • the memory 4 reads only the 0th bit of each of the pixel drive data GD 1,1 to GD n,m one display line at a time, and supplies the respective 0th bits to the column electrode driver circuit 5 as the pixel drive data bits DB1 to DBm.
  • the memory 4 reads, one display line at a time, only the respective first bits of pixel drive data GD 1,1 to GD n,m and supplies these first bits to the column electrode driver circuit 5 as the pixel drive data bits DB1 to DBm.
  • the memory 4 reads only the respective second bits of the pixel drive data GD 1 , 1 to GD n,m one display line at a time and supplies these second bits to the column electrode driver circuit 5 as pixel drive data bits DB1 to DBm. Subsequently, in the subfield SF3, the memory 4 reads only the respective third bits of the pixel drive data GD 1,1 to GD n,m one display line at a time and supplies these third bits to the column electrode driver circuit 5 as pixel drive data bits DB1 to DBm.
  • a drive control circuit 6 generates various timing signals for grayscale-driving the PDP 100 in accordance with the light emission drive sequences shown in the following drawings:
  • the drive control circuit 6 supplies these timing signals to the column electrode driver circuit 5, the row electrode Y driver circuit 7 and the row electrode X driver circuit 8 respectively.
  • a series of driving shown in Figs. 6A to 6H is executed repeatedly.
  • the column electrode driver circuit 5, the row electrode Y driver circuit 7, and the row electrode X driver circuit 8 generate various drive pulses (not shown) to drive the PDP 100 as described below in accordance with the timing signals supplied by the drive control circuit 6, and apply these drive pulses to the column electrodes D 1 to D m , row electrodes X 1 to X n , and row electrodes Y 1 to Y n of the PDP 100, respectively.
  • each of the fields of the video input signal is constituted by the five subfields SF0 to SF4.
  • the leading subfield SF0 sequentially executes a reset step R and an address step W0.
  • the reset step R causes all the discharge cells G (1,1) to G (n,m) of the PDP 100 to perform a reset discharge all together and initializes the discharge cells G (1,1) to G (n,m) in a lit mode (state in which a wall charge of a predetermined amount is formed).
  • the discharge cells G arranged on the first to nth display lines of the PDP 100 are selectively made to perform an erase discharge in accordance with the pixel drive data GD as shown in Fig. 5, in sequence one display line at a time, so that the selected discharge cells are brought into an unlit mode (state where the wall charge has been erased or extinguished).
  • the discharge cells in which the erasure discharge is not induced in this address step W0 retain the state up until immediately before this address step W0, that is, the lit mode.
  • Each of the subfields SF1 to SF3 is further divided into eight subfields SF1 1 to SF1 8 , SF2 1 to SF2 8 , and SF3 1 to SF3 8 respectively.
  • Address steps W1 to W8 are executed in the subfields SF1 1 to SF1 8 , SF2, to SF2 8 , and SF3 1 to SF3 8 respectively.
  • the address step W1 only discharge cells that are arranged in the (8N-7)th display lines (i.e. , the 1st, 9th, 17th, ..., and (n-7)th display lines) among all the discharge cells G (1,1) to G( n,m ) in the PDP 100, are selectively caused to perform an erasure discharge in accordance with the pixel drive data.
  • discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until immediately before the address step W1. That is, the address step W1 sets the discharge cells arranged on the (8N-7)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W2 only the discharge cells arranged on the (8N-6)th display lines (i.e., the 2nd, 10th, 18th, ..., and (n-6)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data.
  • discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until immediately before the address step W2. That is, the address step W2 sets the discharge cells arranged on the (8N-6)th display lines to either the unlit mode or the lit mode in accordance with the pixel drive data.
  • the address step W3 only discharge cells arranged on the (8N-5)th display lines (i.e., the 3rd, 11th, 19th, ..., and (n-5)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data.
  • discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W3. That is, the address step W3 sets the discharge cells arranged on the (8N-5)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W4 only discharge cells arranged on the (8N-4)th display lines (i.e., the 4th, 12th, 20th, ..., and (n-4)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data.
  • discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W4. That is, the address step W4 sets the discharge cells arranged on the (8N-4)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W5 only discharge cells arranged on the (8N-3)th display lines (i.e., the 5th, 13th, 21st, ..., and (n-3)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data.
  • discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W5. That is, the address step W5 sets the discharge cells arranged on the (8N-3)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W6 only discharge cells arranged on the (8N- 2) th display lines (I.e., the 6th, 14th, 22nd,... and (n-2)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data.
  • discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W6. That is, the address step W6 sets the discharge cells arranged on the (8N-2)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W7 only discharge cells arranged on the ( 8N-1 ) th display lines (i.e., the 7th, 15th, 23rd, ..., and (n-1) th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. Discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W7. That is, the address step W7 sets the discharge cells arranged on the (8N-1)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W8 only discharge cells arranged on the (8N)th display lines (i.e., the 8th, 16th, 24th, ..., and nth display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. Discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W8. That is, the address step W8 sets the discharge cells arranged on the (8N)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • a sustain step I which causes only the discharge cells set to the lit mode to discharge light continuously over the period '1', is executed.
  • the drive control circuit 6 performs light emission driving as shown in Figs. 7 to 14 in accordance with the light emission drive sequences shown in Figs. 6A to 6H.
  • a light emission display based on first grayscale driving is executed. Because the 0th bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by the black circles) is induced in the discharge cells in the address step W0 of the subfield SF0, and the discharge cells become the unlit mode.
  • the driving scheme shown in Figs. 6A to 6H the opportunity, in a single field display period, for discharge cells to shift from the unlit mode to the lit mode arises only in the reset step R of the leading subfield SF0. Accordingly, discharge cells that have become the unlit mode retain the unlit state in the course of the single field display period.
  • each discharge cell retains the unlit state in the course of a single field display period, thereby achieving the luminance level (brightness level) 0 as shown in Fig. 15.
  • a light emission display based on second grayscale driving is implemented. Because the first bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in the discharge cells in the address steps W1 to W8 of the subfield SF1. Because discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, sustained discharge light emission is implemented continuously in the sustain steps I that exist in the interval up until the erasure discharge is induced. For example, in the light emission drive sequence shown in Fig. 6A, the address steps are executed as follows:
  • the discharge cells perform a sustained discharge continuously in the sustain steps I of the following subfields:
  • the discharge cells arranged on each display line are each driven at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period, as shown in Fig. 15.
  • the discharge cells arranged on the (8N-7)th display line are at the luminance level '8'; the discharge cells arranged on the (8N-6)th display lines are at the luminance level '5'; the discharge cells arranged on the (8N-5)th display lines are at the luminance level '2'; the discharge cells arranged on the (8N-4)th display lines are at the luminance level '7'; the discharge cells arranged on the (8N-3)th display lines are at the luminance level '4'; the discharge cells arranged on the (8N-2)th display lines are at the luminance level '1'; the discharge cells arranged on the (8N-1)th display lines are at the luminance level '6'; and the discharge cells arranged on the (8N)th display lines are at the luminance level '3'.
  • a light emission display based on third grayscale driving is performed. Because the second bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in each discharge cell in the address steps W1 to W8 of the subfield SF2.
  • the discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, so that sustained discharge light emission is executed continuously in the sustain steps I that exist during the interval up until the erasure discharge is induced.
  • the address steps are executed as follows:
  • the discharge cells perform a sustained discharge continuously in the sustain steps I of the following subfields:
  • the discharge cells arranged on each display line are each driven at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period, as shown in Fig. 15.
  • the discharge cells arranged on the (8N-7)th display lines are at the luminance level '16'; the discharge cells arranged on the (8N-6)th display lines are at the luminance level '13'; the discharge cells arranged on the (8N-5)th display lines are at the luminance level '10'; the discharge cells arranged on the (8N-4)th display lines are at the luminance level '15'; the discharge cells arranged on the (8N-3)th display lines are at the luminance level '12'; the discharge cells arranged on the (8N-2)th display lines are at the luminance level '9'; the discharge cells arranged on the (8N-1)th display lines are at the luminance level '14'; and the discharge cells arranged on the (8N)th display lines are at the luminance level '11'.
  • a light emission display based on fourth grayscale driving is performed as detailed below. Because the third bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in each discharge cell in the address steps W1 to W8 of the subfield SF3.
  • the discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, so that sustained discharge light emission is executed continuously in the sustain steps I that exist during the interval up until the erasure discharge is induced.
  • the address steps are executed as follows:
  • the discharge cells perform a sustained discharge continuously in the sustain steps I of the following subfields.
  • Subfields SF1 1 to SF2 8 and the subfields SF3 1 to SF3 8 for the (8N-7)th display line Subfields SF1 1 to SF2 8 and the subfields SF3 1 to SF3 5 for the (8N-6)th display line; Subfields SF1 1 to SF2 8 and the subfields SF3 1 to SF3 2 for the (8N-5)th display line; Subfields SbF1 1 to SF2 8 and the subfields SF3 1 to SF3 7 for the (8N-4)th display line; Subfields SF1 1 to SF2 8 and the subfields SF3 1 to SF3 4 for the (8N-3)th display line; Subfields SF1 1 to SF2 8 and the subfield SF3 1 for the (8N-2)th display line; Subfields SF1 1 to SF2 8 and the subfield SF3 1 for
  • the discharge cells each emit light at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period, as shown in Fig. 15.
  • the discharge cells arranged on the (8N-7)th display lines are at the luminance level '24'; the discharge cells arranged on the (8N-6)th display lines are at the luminance level '21'; the discharge cells arranged on the (8N-5)th display lines are at the luminance level '18'; the discharge cells arranged on the (8N-4)th display lines are at the luminance level '23'; the discharge cells arranged on the (8N-3)th display lines are at the luminance level '20'; the discharge cells arranged on the (8N-2)th display lines are at the luminance level '17'; the discharge cells arranged on the (8N-1)th display lines are at the luminance level '22'; and the discharge cells arranged on the (8N)th display lines are at the luminance level '19'.
  • a light emission display based on the fifth grayscale driving is implemented. Because all the bits of the pixel drive data GD are logic level 0, erasure discharge is not induced at all during the single field display period. Accordingly, the discharge cells discharge light continuously in the sustain steps I of the subfields SF1 1 to SF1 8 , SF2 1 to SF2 8 , SF3 1 to SF3 8 , and SF4.
  • the discharge cells each emit light at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period as shown in Fig. 15.
  • the discharge cells arranged on the (8N-7)th display lines are at the luminance level '25'; the discharge cells arranged on the (8N-6)th display lines are at the luminance level '25'; the discharge cells arranged on the (8N-5)th display lines are at the luminance level '25'; the discharge cells arranged on the (8N-4)th display lines are at the luminance level '25'; the discharge cells arranged on the (8N-3)th display lines are at the luminance level '25'; the discharge cells arranged on the (8N-2)th display lines are at the luminance level '25'; the discharge cells arranged on the (8N-1)th display lines are at the luminance level '25'; and the discharge cells arranged on the (8N)th display lines are at the luminance level '25'.
  • the first to fifth grayscale driving that is capable of representing luminance corresponding to five levels is executed in accordance with five different pixel drive data GD, namely, '1000', '0100', '0010', '0001', and '0000'.
  • different luminance weightings are applied to eight adjacent display lines, and the eight adjacent display lines are driven at different luminance levels determined by the respective luminance weightings, in each of the first to fifth grayscale driving.
  • luminance weightings ('1' to '8') are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the first field shown in Fig. 6A:
  • the line dither offset value generation circuit 21 adds the line dither offset values LD shown in Fig. 4A to the pixel data PD of the display lines, respectively, as shown in Fig. 16.
  • the line dither offset values LD As a result of this addition of the line dither offset values LD, the following line-offset-added pixel data LF are obtained for each of the display lines, as shown in Fig. 16.
  • (8N-7)th display line the value LF is '010100'; (8N-6)th display line: the value LF is '010111'; (8N-5)th display line: the value LF is '011010'; (8N-4)th display line: the value LF is '010101'; (8N-3)th display line: the value LF is '011000'; (8N-2)th display line: the value LF is '011011'; (8N-1)th display line: the value LF is '010110'; and (8N)th display line: the value LF is '011001'.
  • the lower bit discard circuit 23 discards the lower 3 bits of each of these line-offset-added pixel data LF, thereby obtaining the remaining upper 3 bits of data as the multiple grayscale pixel data MD. That is, as shown in Fig. 16, the following multiple grayscale pixel data MD are obtained for the eight adjacent display lines:
  • pixel drive data GD by the drive data conversion circuit 3.
  • the plasma display device shown in Fig. 3 drives each of the eight adjacent display lines to emit light such that the different line dither offset values LD are added to pixel data PD of the display lines and the different luminance weightings are applied to the display lines.
  • so-called line dither processing which allows the luminance difference between adjacent display lines to be generated, is implemented.
  • the bias of the luminance difference between adjacent display lines of the PDP 100 should be substantially uniform. To this end, the bias is limited to lie within a predetermined value in this embodiment. For example, when '010100' pixel data PD is supplied, the bias of the luminance difference is '2', as shown in Fig. 16.
  • the luminance difference between the (8N-7)th and (8N-6)th display lines is '3'; the luminance difference between the (8N-6)th and (8N-5)th display lines is '5'; the luminance difference between the (8N-5)th and (8N-4)th display lines is '3'; the luminance difference between the (8N-4)th and (8N-3)th display lines is '5'; the luminance difference between the (8N-3)th and (8N-2)th display lines is '3'; the luminance difference between the (8N-2)th and (8N-1)th display lines is '3'; and the luminance difference between the (8N-1)th and (8N)th display lines is '5'.
  • the bias of the luminance difference between the adjacent display lines is equal to or less than '2' in this embodiment.
  • the discharge cells arranged on the (8N-7)th display line are driven to emit light at the luminance level '16' by means of the third grayscale driving
  • the discharge cells arranged on the (8N-6) th display line are driven to emit light at the luminance level '13' by means of the third grayscale driving, or are driven to emit light at the luminance level '21' by means of the fourth grayscale driving.
  • the difference in luminance between the (8N-6)th display line and (8N-7) display line is '3' whereas when the discharge cells on the (8N-6)th display line are driven with the fourth grayscale driving, the luminance difference between the (8N-6)th display line and (8N-7) display line is '5'.
  • the bias of these two luminance differences is therefore '2'.
  • the bias of the luminance differences between adjacent display lines is restricted in a predetermined range, so that a high quality dither-processed image with a smaller luminance bias is expressed.
  • the first to eighth fields of the video input signal constitute one cycle, and the weighting of the line dither processing for each of the eight adjacent display lines is changed for each field as shown in Fig. 17.
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the first to eighth line dither processes are allocated to the display lines as follows:
  • the respective line dither processing is applied alternately to upper and lower display in the screen for each field.
  • the fifth line dither processing which adds a '4' line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ' 4' luminance weighting, is allocated to the (8N-3)th display line in the first field.
  • the fifth line dither processing is performed on the (8N-7)th display line located below the (8N-3)th display line in the screen as indicated by the arrow.
  • the fifth line dither processing is performed on the (8N-1)th display line located above the (8N-7)th display line as shown by the arrow.
  • the fifth line dither processing is performed on the (8N-5)th display line located below the (8N-1)th display line as indicated by the arrow.
  • the fifth line dither processing is performed on the (8N-6)th display line located above the (8N-5)th display line as indicated by the arrow.
  • the fifth line dither processing is performed on the (8N-2)th display line located below the (8N-6)th display line as indicated by the arrow.
  • the fifth line dither processing is performed on the (8N-4)th display line located above the (8N-2)th display line as indicated by the arrow.
  • the fifth line dither processing is performed on the (8N)th display line located below the (8N-4)th display line as indicated by the arrow.
  • the subfield SF1 bears a low-luminance grayscale
  • the subfield SF2 bears a medium-luminance grayscale
  • the subfield SF3 bears a high-luminance grayscale.
  • the subfields SF1, SF2 and SF3 are further divided into the eight subfields SF1 1 to SF1 8 , SF2 1 to SF2 8 , and SF3 1 to SF3 8 respectively, as shown in Fig. 6, for example.
  • the light emission period to be allocated to the subfield SF1 bearing the low-luminance grayscale is short, and therefore cases where the subfield SF1 cannot be divided into eight sometimes arise.
  • Figs. 18A to 18H show examples of the light emission drive sequence of the present invention, which is executed with this point in mind.
  • the drive control circuit 6 supplies, to the column electrode driver circuit 5, the row electrode Y driver circuit 7 and the row electrode X driver circuit 8, various timing signals for grayscale-driving of the PDP 100 in accordance with the light emission drive sequences shown in the following figures in the following fields of the video input signal:
  • the drive control circuit 6 repeatedly executes a series of driving shown in Figs. 18A to 18H.
  • Each of the column electrode driver circuit 5, the row electrode Y driver circuit 7, and the row electrode X driver circuit 8 generates various drive pulses (not shown) that are utilized to drive the PDP 100 as described below in accordance with the timing signals supplied by the drive control circuit 6, and applies these drive pulses to the column electrodes D 1 to D m , row electrodes X 1 to X n , and row electrodes Y 1 to Y n of the PDP 100.
  • each of the fields of the video input signal is divided into five subfields SF0 to SF4.
  • the leading subfield SF0 sequentially executes a reset step R and an address step W0.
  • the reset step R causes all the discharge cells G (1,1) to G (n,m) of the PDP. 100 to perform a reset discharge all together and initializes the discharge cells G (1,1) to G (n,m) in the lit mode (state in which a wall charge of a predetermined amount is formed).
  • the discharge cells G arranged on the first to nth display lines of the PDP 100 are selectively made to perform an erase discharge in accordance with the pixel drive data GD as shown in Fig. 5, in sequence one display line at a time, to make the transition to the unlit mode (state where the wall charge has been erased) .
  • the discharge cells in which an erasure discharge is not induced in this address step W0 retain their state up until immediately before this address step W0, that is, the lit mode.
  • the subfield SF1 is further divided into four subfields SF1 1 to SF1 4 respectively.
  • the subfield SF2 is divided into eight subfields SF2 1 to SF2 8
  • the subfield SF3 is divided into eight subfields SF3 1 to SF3 8 .
  • a sustain step I in which only the discharge cells set to the lit mode are made to discharge light continuously over period '1', and address steps W1 to W8 as described below are executed in the subfields SF1 to SF3 respectively.
  • the address step W1 only those discharge cells that are arranged on the (8N-7)th display lines, namely the 1st, 9th, 17th, ..., and (n-7)th display lines, among all the discharge cells G (1,1) to G (n,m) formed in the PDP 100, are selectively caused to perform an erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until immediately before the address step W1. That is, the address step W1 sets the discharge cells arranged on the (8N-7)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W2 only those discharge cells arranged on the (8N-6)th display lines, namely the 2nd, 10th, 18th, ..., and (n-6)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until immediately before the address step W2. That is, the address step W2 sets the discharge cells arranged on the (8N-6)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • address step W3 only discharge cells arranged on the (8N-5)th display lines, namely the 3rd, 11th, 19th, ..., and (n-5)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W3.
  • the address step W3 sets the discharge cells arranged on the (8N-5)th display lines to either the unlit or the lit mode in accordance with the pixel drive data.
  • address step W4 only discharge cells arranged on the (8N-4)th display lines, namely the 4th, 12th, 20th, ..., and (n-4)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W4.
  • the address step W4 sets the discharge cells arranged on the (8N-4)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W5 only those discharge cells arranged on the (8N-3)th display lines, namely the 5th, 13th, 21st, ..., and (n-3)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W5. That is, the address step W5 sets the discharge cells arranged on the (8N-3)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W6 only those discharge cells arranged on the (8N-2)th display lines, namely the 6th, 14th, 22nd,.., and (n-2)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W6.
  • the address step W6 sets the discharge cells arranged on the (8N-2)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W7 only the discharge cells arranged on the (8N-1)th display lines, namely the 7th, 15th, 23rd, ..., and (n-1)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W7. That is, the address step W7 sets the discharge cells arranged on the (8N-1)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W8 only the discharge cells arranged on the (8N)th display lines, namely the 8th, 16th, 24th, ..., and nth display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data.
  • the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W8.
  • the address step W8 sets the discharge cells arranged on the (8N) th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the drive control circuit 6 performs light emission driving as shown in Figs. 19 to 26 in accordance with the light emission drive sequences shown in Figs. 18A to 18H.
  • a light emission display based on first grayscale driving as detailed below is executed. Because the 0th bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by the black circles) is induced in the discharge cells in the address step W0 of the subfield SF0, and the discharge cells make the transition to the unlit mode.
  • the opportunity, in a single field display period, for discharge cells to make the transition from the unlit mode to the lit mode state arises only in the reset step R of the leading subfield SF0. Accordingly, discharge cells that have made the transition to the unlit mode retain the unlit state throughout the single field display period.
  • each discharge cell retains an unlit state throughout a single field display period, so that driving at the luminance level 0 is implemented as shown in Fig. 27.
  • a light emission display based on second grayscale driving is implemented as detailed below.
  • the first bit of the pixel drive data GD is logic level 1
  • an erasure discharge (indicated by overlapping circles) is induced in the discharge cells in the address steps W1 to W8 of the subfield SF1.
  • the discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0 so that sustained discharge light emission is implemented continuously in sustain steps I that exist in the interval up until the erasure discharge is induced. Therefore, for example, in the light emission drive sequence shown in Fig. 18A, the discharge cells on the display lines perform a sustained discharge continuously in the sustain step I of each of the following subfields:
  • the discharge cells arranged on each display line are each driven to emit light at a luminance level that corresponds with the period of the light emission generated by the sustained discharge induced during the single field display period. Specifically, as shown in Fig.
  • the discharge cells arranged on the (8N-7)th display line are at luminance level '4'; the discharge cells arranged on the (8N-6)th display line are at luminance level '3'; the discharge cells arranged on the (8N-5)th display line are at luminance level '1': the discharge cells arranged on the (8N-4)th display line are at luminance level '4'; the discharge cells arranged on the (8N-3)th display line are at luminance level '2'; the discharge cells arranged on the (8N-2)th display line are at luminance level '1': the discharge cells arranged on the (8N-1)th display line are at luminance level '3'; and the discharge cells arranged on the (8N)th display line are at luminance level '2'.
  • a light emission display based on third grayscale driving is implemented as detailed below.
  • the erasure discharge (indicated by overlapping circles) is induced in the discharge cells in address steps W1 to W8 of the subfield SF2.
  • the discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0 so that sustained discharge light emission is implemented continuously in sustain steps I that exist in the interval up until the erasure discharge is induced.
  • the discharge cells on the display lines perform a sustained discharge continuously in the sustain step I of each of the following subfields:
  • the discharge cells arranged on the respective display lines are each driven at a luminance level that corresponds with the period of the light emission generated by the sustained discharge induced during the single field display period, that is, as shown in Fig.
  • the discharge cells arranged on the (8N-7)th display line are at luminance level '12'; the discharge cells arranged on the (8N-6)th display line are at luminance level '9'; the discharge cells arranged on the (8N-5)th display line are at luminance level '6'; the discharge cells arranged on the (8N-4)th display line are at luminance level '11'; the discharge cells arranged on the (8N-3)th display line are at luminance level '8'; the discharge cells arranged on the (8N-2)th display line are at luminance level '5'; the discharge cells arranged on the (8N-1)th display line are at luminance level '10'; and the discharge cells arranged on the (8N)th display line are at luminance level '7'.
  • a light emission display based on fourth grayscale driving is performed as detailed below.
  • the erasure discharge (indicated by overlapping circles) is induced in each discharge cell in the address steps W1 to W8 of the subfield SF3.
  • the discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, and then sustained discharge light emission is executed continuously in sustain steps I that exist during the interval up until the erasure discharge is induced.
  • the discharge cells on the display lines perform a sustained discharge continuously in the sustain step I of each of the following subfields:
  • the discharge cells each emit light at a luminance level corresponding with the period of the light emission generated by the sustained discharge induced in the course of a single field display period, that is, as shown in Fig. 27:
  • a light emission display based on the fifth grayscale driving is implemented as detailed below. Because all the bits of the pixel drive data GD are logic level 0, the erasure discharge is not induced at all during the single field display period. Accordingly, the discharge cells discharge light continuously in the sustain steps I of the subfields SF1 1 to SF1 4 , SF2 1 to SF2 8 , SF3 1 to SF3 8 , and SF4.
  • the discharge cells each emit light at a luminance level corresponding with the period of the light emission generated by the sustained discharge induced in the course of a single field display period. Specifically, as shown in Fig. 27, the discharge cells arranged on the respective display lines all emit light at the luminance level '21'.
  • the number of divisions (four) of the subfield (SF1) bearing the low luminance grayscale is smaller than the number of divisions (eight) in the other subfields. Further, the order of execution of the address steps executed in the subfield bearing the low luminance grayscale is the same as in the case of the other subfields.
  • the present invention can also be applied to a case of adopting so-called selective write addressing, in which all the discharge cells are preset to the unlit mode and discharge cells are selectively made to make the transition to the lit mode in accordance with pixel data.
  • Fig. 28 shows a light emission drive sequence used when implementing the driving in the first field as shown in Fig. 18A by adopting selective write addressing.
  • Fig. 29 shows light emission drive patterns performed on the basis of the light emission drive sequences shown in Figs. 18E to 18H.
  • the drive data conversion circuit 3 shown in Fig. 3 converts multiple grayscale pixel data MD into 4-bit pixel drive data GD in accordance with the data conversion table shown in Fig. 29.
  • the drive control circuit 6 implements light emission drive control on the basis of the light emission drive sequence as shown in Fig. 28 in the initial first field, in accordance with this pixel drive data GD.
  • the reset step R, address step W0 and sustain step I are executed in sequence in the leading subfield SF4.
  • the reset step R shown in Fig. 28 causes all the discharge cells G (1,1) to G (n,m) of the PDP 100 to perform a reset discharge all together and initializes the discharge cells G (1,1) to G (n,m) in the unlit mode (state in which a wall charge does not exist).
  • the discharge cells G arranged on the first to nth display lines of the PDP 100 are selectively made to perform a write discharge in accordance with the pixel drive data GD as shown in Fig.
  • subfields SF3 1 to SF3 8 , SF2 1 to SF2 8 , and SF1 1 to SF1 4 are executed in sequence.
  • the address steps W1 to W8 are executed as detailed below in the subfields SF3 to SF1.
  • the address step W1 only those discharge cells that are arranged on the (8N-7)th display lines, namely the 1st, 9th, 17th, ..., and (n-7)th display lines, among all the discharge cells G (1,1) to G (n,m) formed in the PDP 100, are selectively caused to perform a write discharge in accordance with the pixel drive data.
  • the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until immediately before the address step W1.
  • the address step W1 sets the discharge cells arranged on the (8N-7)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W4 sets the discharge cells arranged on the (8N-4)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W7 only discharge cells arranged on the (8N-1)th display line, namely the 7th, 15th, 23rd, ..., and (n-1)th display lines, are selectively made to perform a write discharge in accordance with the pixel drive data.
  • the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W7.
  • the address step W7 sets the discharge cells arranged on the (8N-1)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W2 sets the discharge cells arranged on the (8N-6)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W5 sets the discharge cells arranged on the (8N-3)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W8 only the discharge cells arranged on the (8N)th display lines, namely the 8th, 16th, 24th, ..., and nth display lines, are selectively made to perform the write discharge in accordance with the pixel drive data.
  • the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W8.
  • the address step W8 sets the discharge cells arranged on the (8N) th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W3 sets the discharge cells arranged on the (8N-5)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the address step W6 only the discharge cells arranged on the (8N-2)th display lines, namely the 6th, 14th, 22nd,... , and (n-2)th display lines, are selectively made to perform the write discharge in accordance with the pixel drive data.
  • the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W6.
  • the address step W6 sets the discharge cells arranged on the (8N-2)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
  • the sustain step I in which only those discharge cells in the lit mode are made to emit light by performing a sustained discharge continuously over the light emission period '1', is executed directly after the address steps W1 to W8.
  • Whether or not the write discharge should be induced in the address steps W1 to W8 of the respective subfields SF1 to SF4 is determined by the bits of the pixel drive data GD shown in Fig. 29. Specifically, the occurrence of the write discharge in the subfield SF4 is determined by the 0th bit of the pixel drive data GD, the occurrence of the write discharge in the subfield SF3 is determined by the first bit of the pixel drive data GD, the occurrence of the write discharge in the subfield SF2 is determined by the second bit of the pixel drive data GD, and the occurrence of the write discharge in the subfield SF1 is determined by the third bit of the pixel drive data GD.
  • the initial write discharge (indicated by overlapping circles) is induced in the discharge cells within the single field display period, and, once set to the lit mode, the state is retained until the final subfield SF1 4 and a sustained discharge (indicated by a white circle) is executed continuously in the sustain steps I that exist in this interval.
  • the number of divisions of the subfield SF1 is not limited to four.
  • the subfield SF1 may be divided:

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)
EP04014739A 2003-07-02 2004-06-23 Verfahren zum Steuern einer Anzeigetafel Withdrawn EP1494198A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003190284 2003-07-02
JP2003190284A JP4490656B2 (ja) 2003-07-02 2003-07-02 表示パネルの駆動方法

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EP1494198A2 true EP1494198A2 (de) 2005-01-05
EP1494198A3 EP1494198A3 (de) 2008-03-26

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KR (1) KR100590300B1 (de)
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TW (1) TW200504647A (de)

Cited By (2)

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EP1615198A3 (de) * 2004-07-08 2008-03-19 Pioneer Corporation Verfahren zur Steuerung einer Anzeigetafel
EP1492075A3 (de) * 2003-06-23 2008-03-26 Pioneer Corporation Ansteuerschaltung für eine Anzeigetafel

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Publication number Priority date Publication date Assignee Title
AU2003300744A1 (en) * 2003-12-22 2005-07-14 Telecom Italia S.P.A. Method, system and computer program for planning a telecommunications network
JP4731841B2 (ja) * 2004-06-16 2011-07-27 パナソニック株式会社 表示パネルの駆動装置及び駆動方法
KR102395792B1 (ko) * 2017-10-18 2022-05-11 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

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JP3423865B2 (ja) * 1997-09-18 2003-07-07 富士通株式会社 Ａｃ型ｐｄｐの駆動方法及びプラズマ表示装置
JP3789052B2 (ja) * 1998-12-03 2006-06-21 パイオニア株式会社 プラズマディスプレイパネルの駆動方法
JP3459890B2 (ja) * 1999-09-22 2003-10-27 Ｎｅｃ液晶テクノロジー株式会社 疑似中間処理回路の初期化方法
JP3961171B2 (ja) * 1999-11-24 2007-08-22 パイオニア株式会社 ディスプレイ装置の多階調処理回路
JP2002006800A (ja) * 2000-06-21 2002-01-11 Pioneer Electronic Corp プラズマディスプレイパネルの駆動方法
JP2002082647A (ja) * 2000-09-05 2002-03-22 Hitachi Ltd 表示装置および表示方法
FR2816439A1 (fr) * 2000-11-08 2002-05-10 Thomson Plasma Procede de balayage d'un panneau de visualisation d'images a vibration continue du nombre de bits de codage de la luminance
AUPR234700A0 (en) * 2000-12-29 2001-01-25 Canon Kabushiki Kaisha Error diffusion using next scanline error impulse response
JP2002341381A (ja) * 2001-05-18 2002-11-27 Matsushita Electric Ind Co Ltd 薄膜トランジスタアレイとそれを用いた液晶表示装置
JP2003091258A (ja) * 2001-07-09 2003-03-28 Matsushita Electric Ind Co Ltd プラズマディスプレイパネル駆動方法及びプラズマディスプレイパネル駆動装置
EP1291835A1 (de) * 2001-08-23 2003-03-12 Deutsche Thomson-Brandt Gmbh Verfahren und Vorrichtung zur Videobildbearbeitung
JP4410997B2 (ja) * 2003-02-20 2010-02-10 パナソニック株式会社 表示パネルの駆動装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1492075A3 (de) * 2003-06-23 2008-03-26 Pioneer Corporation Ansteuerschaltung für eine Anzeigetafel
US7453477B2 (en) 2003-06-23 2008-11-18 Pioneer Corporation Driving device for a display panel
EP1615198A3 (de) * 2004-07-08 2008-03-19 Pioneer Corporation Verfahren zur Steuerung einer Anzeigetafel
US7501997B2 (en) 2004-07-08 2009-03-10 Pioneer Corporation Method of driving a display panel

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US7317431B2 (en) 2008-01-08
KR100590300B1 (ko) 2006-06-19
KR20050004092A (ko) 2005-01-12
JP4490656B2 (ja) 2010-06-30
CN1577426A (zh) 2005-02-09
EP1494198A3 (de) 2008-03-26
TW200504647A (en) 2005-02-01
JP2005024901A (ja) 2005-01-27
US20050057452A1 (en) 2005-03-17

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