Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/01—Manufacture or treatment
  • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/80—Heterojunction BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/80—Heterojunction BJTs
  • H10D10/821—Vertical heterojunction BJTs
  • H10D10/891—Vertical heterojunction BJTs comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/10—Semiconductor bodies
  • H10F77/12—Active materials

Definitions

• the invention relates to silicon germanium (SiGe) heterojunction bipolar transistors
• This bandgap offset provides the unique advantages of the SiGe HBT by creating a grading field in the base to enhance carrier diffusion across the base and thus improve transistor speed.
• SiGe HBTs have been used as transistors for small signal amplifiers (i.e. switching approximately 5 volts or less) to provide the switching speeds (above 1GHz) necessary for current wireless communications devices.
• One of the difficulties encountered by the inventors in utilizing SiGe HBTs for small signal amplifiers is that the common emitter output characteristics (i.e. the collector current versus the collector-emitter voltage) for such amplifiers generally exhibit poor Early voltage.
• Fig. la (Prior Art) illustrates the Early voltage for SiGe HBTs without use of the invention. The individual curves indicate the output characteristics for different applied base voltages; the higher the curve, the higher the applied base voltage. Note that as applied base current increases, the slope of the curves become more vertical.
• N A is a key indicator of the current gain cutoff frequency (f ⁇ ) for a SiGe HBT.
• f ⁇ current gain cutoff frequency
• the invention is a SiGe HBT comprising a SiGe layer having a thickness and Ge concentration greater than the SiGe stability limit, and a plurality of misfit dislocations therein that do not create appreciable charge trapping sites.
• the invention is a SiGe HBT with an SiGe layer that has a thickness of at least approximately 70nm and a Ge concentration of at least 10% on a plurality of isolation structures, a base/collector junction above the isolation structures, and a plurality of misfit dislocations that do not appreciably extend above the base/collector junction.
• the invention is a bipolar transistor for a small signal amplifier that has a cutoff frequency of at least approximately 19 GHz, a SiGe layer having a thickness and a Ge content that is greater than the SiGe stability limit, a plurality of isolation regions abutting said collector region, and a base region formed on said collector region, said SiGe layer having a plurality of misfit dislocations therein adjacent said plurality of isolation regions and extending into said collector region without substantially extending into said base region.
• the invention is a method of forming a bipolar transistor, comprising the steps of forming a plurality of isolation regions in a silicon substrate; forming a SiGe layer on said substrate and said isolation regions, said SiGe layer having a thickness and a Ge content that is greater than the SiGe stability limit; and doping said SiGe layer and the substrate with a first dopant to form a collector region, wherein said collector region comprises a plurality of misfit dislocations that do not substantially extend beyond said collector region into other portions of the bipolar transistor.
• Fig. la is plot of IC versus NCE for an experimental SiGe HBT
• Fig. lb is plot of IC versus VCE for an SiGe HBT of the present invention
• Figure 2 shows a plot of collector current density versus cutoff frequency for ⁇ P ⁇ s shown with the Early voltages shown in Figs, la and lb, respectively;
• Fig. 3 is a plot of SiGe concentration versus thickness, showing various experimental data points that include those of the invention, superimposed on the SiGe stability curves reported by prior art articles;
• Fig. 4 is a cross-sectional view of a SiGe HBT constructed in accordance with the teachings of a first embodiment of the invention;
• Fig. 5 shows the Gummel plots (IC, IB vs NCE) of the ⁇ P ⁇ s shown with the Early voltages shown in Figs, la and lb, respectively;
• Fig. 6 is a plot of normalized yield data for SiGe HBTs of the thicknesses shown by the data points in Fig. 3;
• Fig. 7 is a graph illustrating three embodiments of Ge concentration versus layer thickness for the SiGe layer of the invention. Best Mode For Carrying Out The Invention The present inventors found that Early voltage (and hence cutoff frequency) can be substantially enhanced by increasing the thickness of the SiGe layer. While in the prior art it is known to increase SiGe thickness for other purposes, thicker SiGe layers are generally avoided for fear of creating misfit dislocations. As will be explained in more detail below, the present inventors have found that when managed properly, misfit dislocations do not adversely affect the performance or yield of the resulting SiGe HBTs.
• SiGe enhances charge mobility by introducing mechanical strain due to the lattice mismatches inherent in the Si-Ge compound.
• the accepted wisdom in the art is that the resulting crystal dislocations will reduce both performance and yield.
• the performance penalty would be due to dislocations relieving the mechanical stresses that create the bandgap offsets that SiGe provides.
• the yield penalty would be due to the defects disturbing the crystallography of the substrate.
• SiGe stability limits The different SiGe stability limits reported by Matthews-Blakesley and Stiffler are plotted in Fig. 3, which shows the reported optimal relationships between SiGe thickness and Ge concentration.
• the SiGe HBT of the invention is formed on a monocrystalline silicon substrate 10 having shallow trench isolation regions (STI) 12 therein.
• An SiGe layer 14 is epitaxially grown using conventional techniques on the substrate 10, to a thickness t of at least 40nm and a Ge concentration of at least approximately 10%.
• the SiGe layer is insitu doped during growth with boron to form a base region 14B (not shown to scale laterally). Note that as a practical matter boron from the base region can diffuse deeper into the SiGe layer during various processing thermal cycles, from a depth X to a depth Y into the SiGe layer 14. As such, the resulting base/collector junction can be at JA or JB.
• Figure 2 shows a plot of collector current density versus cutoff frequency for (a) an NPN with Early voltages as shown in Fig. la (indicated by the dashed line); and (b) the NPN with the Early voltages shown in Fig. lb (indicated by the solid line).
• An aspect of the invention is that these gains in Early voltage and cutoff frequency do not come at the expense of dislocations that decrease performance (by charge trapping) or yield (by crystal dislocations).
• Fig. 5 shows the Gummel plots (IC, IB vs VCE) of the NPNs shown with the Early ⁇ voltages shown in Figs, la and lb, respectively. Note that the IB and IC curves in the Gummel plots have ideal slopes (n ⁇ l (n is a measure of ideality) or 60 mV/decade at room temperature) which indicates that there was no substantial charge trapping induced by the misfit dislocations formed as part of the thicker SiGe layer.
• Fig. 6 shows a plot of normalized yields for SiGe HBTs of the invention, for different SiGe thicknesses.
• the first region shown thickness of 300 angstroms, Ge concentration of 10%
• Fig. 2 shows the upper limit of the SiGe stability curves (see Fig. 2).
• Fig. 7 is a plot of Ge concentration percentage versus depth of a 70nm thick SiGe layer, for three embodiments of the present invention.
• the Ge concentration in the SiGe layer of the invention is approximately 10% throughout the thickness of the 40nm-thick SiGe film.
• This embodiment produced the collector current versus the collector-emitter voltage plot of the invention as shown by the solid lines of Fig. 3.
• the Ge concentration in the SiGe layer of the invention is approximately 10% throughout the thickness of the 70nm-thick film.
• the first and second embodiments produced the yield data shown in Fig. 6.
• the ideal Gummel plots indicate that the resulting dislocations did not establish appreciable charge trapping sites.
• the inventors have found that SiGe layers that have misfit dislocations can improve performance without degrading yield.
• the inventors have found that the large numbers of misfit dislocations, in and of themselves, are not determinative of performance or yield. Rather, the key is that the dislocations do not create appreciable charge trapping, and do not extend in large numbers past the base/collector junction.
• the invention has applicability to electrical circuits and devices, especially those used in communication systems.

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• 2002
  • 2002-04-26 WO PCT/US2002/013315 patent/WO2003092079A1/en not_active Ceased
  • 2002-04-26 CN CNA028287622A patent/CN1625811A/zh active Pending
  • 2002-04-26 KR KR1020047016720A patent/KR100754561B1/ko not_active Expired - Fee Related
  • 2002-04-26 JP JP2004500339A patent/JP4223002B2/ja not_active Expired - Fee Related
  • 2002-04-26 EP EP02734064A patent/EP1502308A4/de not_active Withdrawn
  • 2002-04-26 AU AU2002305254A patent/AU2002305254A1/en not_active Abandoned

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