EP1559196A2 - Tampon de sortie a commande rapide - Google Patents

Tampon de sortie a commande rapide

Info

Publication number
EP1559196A2
EP1559196A2 EP03759287A EP03759287A EP1559196A2 EP 1559196 A2 EP1559196 A2 EP 1559196A2 EP 03759287 A EP03759287 A EP 03759287A EP 03759287 A EP03759287 A EP 03759287A EP 1559196 A2 EP1559196 A2 EP 1559196A2
Authority
EP
European Patent Office
Prior art keywords
transistor
terminal
control circuit
controlled
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03759287A
Other languages
German (de)
English (en)
Other versions
EP1559196A4 (fr
Inventor
Lorenzo Bedarida
Stefano Sivero
Davide Manfre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/323,614 external-priority patent/US6734701B2/en
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP1559196A2 publication Critical patent/EP1559196A2/fr
Publication of EP1559196A4 publication Critical patent/EP1559196A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Definitions

  • the invention relates to output buffers, and particularly to controlling an internal VDDQ reference voltage around a target value when short capacitor charge times are desired.
  • an internal power source may be viewed as an RLC model (resistance-inductance-capacitance) between an external pin and integrated transistors.
  • RLC model resistance-inductance-capacitance
  • Figure 1 shows an external voltage or VDDQ GEN (or VDDQ_GEN in Figure 1) connected through inductance L to resistors R inhabit ..., R n and capacitors C Recipe ..., C n , wherein the capacitors C réelle ..., C n power the internal voltages or VDDQ ⁇ nterna ⁇ (or INTERNAL_VDDQ) in Figure 1).
  • problems are observed as being caused by inductance and resistance when it is desired to charge a relatively large capacitance in a very short time, i.e., on the order of nanoseconds (ns).
  • This undesired effect may occur due to delays associated with waiting for the VDDQ to recover before detecting the V ou , logic value to be "1".
  • the charging and discharging of the output data pin i.e., characterized by a relatively large capacitance, is one of the situations wherein this effect may produce significant undesirable effects.
  • current control may be provided when the output buffers are switching on.
  • the control of the VDDQ absorbed current may be achieved by different techniques.
  • One technique is controlling the p-mos buffer turn on.
  • the buffer elements are not switched on in digital mode, as is typical with traditional architectures, but their VGS absolute values rise in time with a pending control.
  • Figure 2 e.g., schematically illustrates a conventional architecture.
  • the conventional architecture of Figure 2 has VDDQ internal connected to the p-mos (P4) transistors M 0 and M 3 .
  • the p-mos transistor M 3 is connected to n-mos (N) transistor M 2 .
  • the p-mos transistor M 0 is connected to n-mos (N) transistor M,.
  • the n-mos transistors M, and M 2 are each also connected to ground.
  • An input control signal data om (or OUT_DATA in Figure 2) controls each of the p-mos transistor M 3 and the n-mos transistor M 2 .
  • the output of the p-mos transistor M 3 controls each of p-mos transistor M 0 and n-mos transistor M,.
  • the output of the p-mos transistor M 0 is connected to capacitor C out .
  • the discharge current may be controlled, as in the circuit of Figure 2, by the turning to ground of the gate of the p-mos transistor M 0 when data out is low. In this way, current absorbed by the out buffer, when the output data changes from "0" to "1", has a continuous profile in the time without abrupt variations.
  • the discharge resistor (RP) R may be inserted between the output of the p-mos transistor M 10 corresponding to the p-mos transistor M 3 of Figure 2, and the n-mos transistor M g corresponding to the n-mos transistor M 2 of Figure 2.
  • the output of p-mos transistor M 10 would still control the p-mos (P4) transistor M,, corresponding to the p- mos transistor M 0 of Figure 2.
  • the n-mos transistor (N) M 9 of the circuit of Figure 4, and corresponding to the n-mos transistor M, of Figure 2, would be controlled by digital N- control, rather than by the output of p-mos transistor M, 0 as in the circuit of Figure 2.
  • the mirrored current transistor M 16 may be inserted between the output of the p-mos transistor M 14 corresponding to the p-mos transistor M 3 of Figure 2, and the n-mos transistor M 12 corresponding to the n-mos transistor M 2 of Figure 2.
  • the mirrored current transistor M 16 is controlled by I mirror (or I_MIRROR in Figure 5).
  • the output of p-mos transistor M 14 would still control the p-mos (P4) transistor M 15 corresponding to the p-mos transistor M 0 of Figure 2.
  • the n-mos transistor (N) M 13 of the circuit of Figure 5 would be controlled by digital N-control, rather than by the output of p- mos transistor M 14 as in the circuit of Figure 2.
  • an output buffer switch-on control is provided for avoiding internal VDDQ drop and overshoot with a limited circuital overhead.
  • Eventual VDDQ variations are automatically corrected by active controlling implemented by an output voltage feedback arrangement.
  • a particularly preferred output buffer switch-on control circuit includes at least four transistors.
  • the first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source.
  • the second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor.
  • the second transistor also has a second terminal connected to a first terminal of an output capacitor.
  • the third transistor is controlled by the output data source and has a first terminal connected to a common voltage.
  • the fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor and has a second terminal connected to the common voltage.
  • the switch-on control circuit further includes a discharge current control circuit connected between a second terminal of the first transistor and a second terminal of the third transistor.
  • the discharge current control circuit is advantageously preferably actively-controlled.
  • the discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor.
  • the mirrored current transistor is preferably controlled by a connection between the second terminal of the second transistor and the first terminal of the fourth transistor.
  • the mirrored current transistor preferably includes a first terminal connected to the second terminal of the first transistor and preferably also includes a second terminal connected to the discharge resistor.
  • the discharge resistor is preferably connected between the mirrored current transistor and the third transistor.
  • the first and second transistors preferably comprise p-type MOSFETS, and the third and fourth transistors comprise n-type MOSFETS.
  • a second terminal of the output capacitor is preferably connected to the common voltage.
  • Figure 1 schematically illustrates a schematic representation of a simplified RLC model illustrating an output buffer between an external pin and transistors of an integrated device.
  • Figure 2 schematically illustrates a conventional current control for the switching on of output buffers.
  • Figure 3 schematically illustrates a modified current control for the switching on of output buffers including a discharge current control device.
  • Figure 4 schematically illustrates a discharge resistor as an example of the discharge current control device of Figure 3.
  • Figure 5 schematically illustrates a mirrored current transistor as another example of the discharge current control device of Figure 3.
  • Figure 6 schematically illustrates a drop controller transistor and discharge resistor combination with output voltage feedback according to a preferred embodiment.
  • Figure 7 shows comparative simulation plots of VDDQ voltage versus time for a switch-on circuit with conventional discharge current control and for a switch-on circuit with discharge current control according to a preferred embodiment, along with a plot of the simulated V out for the output capacitor used for generating the VDDQ plots.
  • Figure 8 shows comparative plots of VDDQ voltage versus time for a switch-on circuit with conventional discharge current control and for a switch-on circuit with discharge current control according to a preferred embodiment, along with comparative plots of V out for the output capacitor also for each of a switch-on circuit with conventional discharge current control and for a switch-on circuit with discharge current control according to a preferred embodiment.
  • the output buffer switch-on control circuit of the preferred embodiment includes a discharge current control circuit which is preferably actively-controlled.
  • the preferred discharge current control circuit solves the VDDQ overshoot problem described in the background.
  • the control of the VDDQ drop is preferably active.
  • a p-mos transistor is inserted into the gate discharge path. This transistor is controlled by the V out voltage (or C out in Figure 6).
  • a first p-mos transistor M 19 has a first terminal connected to VDDQ ⁇ nternal .
  • the first p-mos transistor M 19 is controlled by data oul , as shown.
  • a second p-mos transistor M 20 has a first terminal also connected to VDDQ ⁇ nlinda ⁇ .
  • the second p-mos transistor M 20 is controlled by connection to the second terminal of the first p-mos transistor M 19 .
  • a first n-mos transistor M l7 is also controlled by data out , and has a first terminal connected to a common voltage, such as ground.
  • a second n-mos transistor M 18 is digital N- controlled, has a first terminal connected to the second terminal of the second p-mos transistor M 20 , and has a second terminal connected the common voltage.
  • the preferred discharge current control circuit includes a mirrored current, preferably of p-mos type, transistor M 2 , that is feedback controlled by V out (or C out in Figure 6).
  • the second terminal of the second p-mos transistor M 20 and first terminal of the second n-mos transistor M, 8 are each also preferably connected to V out (or C out ), and thus also to the gate of the mirrored current p-mos transistor M 21 .
  • the preferred discharge current control circuit further preferably includes a discharge resistor R 5 .
  • the mirrored current transistor M 21 has a first terminal connected to the second terminal of the first p-mos transistor M 19 which controls the second p-mos transistor M 20 .
  • the second terminal of the mirrored current transistor M 2l is connected to the discharge resistor R 5 .
  • the discharge resistor R 5 is, in turn, connected between the mirrored current transistor M 21 and the second terminal of the first n- mos transistor M 17 .
  • the buffer gate discharge current is defined by the resistor "R” and the p-mos “P” resistance, as shown in respective circles in Figure 6.
  • An eventual VDDQ drop is immediately stopped by the resistance of the p-mos transistor M 2 , which rises with the value of V out (or C out ).
  • the drop control is "active", because it depends on the value of V out (or C out ), which rises in time. The system is able to autorecover these VDDQ drop problems.
  • the rise of V ou[ (C out ) induces a proportional turn off of the mirrored current transistor M 21 , or p-mos "P" of Figure 6, which "brakes" the switching-on of the output buffer.
  • the current which charges the C out output capacitor decreases in the time with a limitation on the VDDQ overshoot value.
  • the output buffer switch-on control circuit generally depends on the RLC value of VDDQ out according to the model schematically illustrated at Figure 1.
  • the switch- on technique may be varied by employing a group of fuses to adapt switch-on circuit to real requirements of a physical device.
  • Figure 7 shows comparative simulation plots of VDDQ voltage versus time.
  • Plot A of Figure 7 shows a VDDQ plot for a switch-on circuit with conventional discharge current control, e.g., such as that described above with reference to Figure 2.
  • Plot B of Figure 7 shows a VDDQ plot for a switch-on circuit with discharge current control according to a preferred embodiment, e.g., such as that described herein with reference to Figure 6.
  • Plot C of Figure 7 shows a plot of a digital signal used as an enable command for changing the value of the output that was used in generating the simulation plots A and B.
  • the capacitance of the C out capacitor was 50 pF
  • external VDDQ was 2.2 V
  • T - 40° C.
  • the voltage of plot B according to the circuit of the preferred embodiment exhibits greater stability and reduced fluctuations than the voltage of plot A according to the conventional circuit.
  • the VDDQ drop has the same value, i.e., from 2.2 to 1.4, in both plot A and plot B.
  • the p-mos controller induces an evident decrement in the duration of the VDDQ undershoot time.
  • An analogue improvement is visible for the overshoot control.
  • plot B according to the circuit of the preferred embodiment is practically free of VDDQ overshoot, while plot A according to the conventional circuit exhibits a very large overshoot.
  • Figure 8 shows further comparative plots of VDDQ voltage versus time.
  • Plot A shows voltage versus time for a switch-on circuit with conventional discharge current control.
  • Plot B shows voltage versus time for a switch-on circuit with discharge current control according to a preferred embodiment.
  • Figure 8 also shows comparative plots of V out for the output capacitor.
  • Plot C shows V out versus time for a switch-on circuit with conventional discharge current control.
  • Plot D shows V out versus time for a switch-on circuit with discharge current control according to a preferred embodiment.
  • a digital signal was used as an enable command for changing the value of the output.
  • Dimensions of the uncontrolled buffer are those limiting VDDQ drop.
  • Figure 8 illustrates that with a comparable VDDQ drop and overshoot for the conventional case (plot A) and for the circuit of the preferred embodiment (plot B), controlling the V out rise is quicker the p-mos discharge gate controller of the preferred embodiment.
  • the time to charge C out to the trigger point voltage i.e., VDDQ/2 is shown as being about 20% faster for the circuit of the preferred embodiment compared with the conventional circuit.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

Cette invention se rapporte à un circuit de commande de mise sous tension à tampon de sortie, qui comprend plusieurs transistors et un circuit de commande à courant de décharge. Un premier transistor possède une première borne connectée à une ligne de tension interne et il est commandé par une source de données de sortie. Un second transistor possède une première borne connectée à une ligne de tension interne et il est commandé par une seconde borne du premier transistor. Le second transistor possède également une seconde borne connectée à une première borne d'un condensateur de sortie. Un troisième transistor est commandé par la source de données de sortie et il possède une première borne connectée à une tension commune. Un quatrième transistor est commandé en mode numérique et il possède une première borne connectée à la seconde borne du second transistor. Le quatrième transistor comporte également une seconde borne connectée à la tension commune. Ce circuit de commande à courant de décharge est de préférence commandé en mode actif et il est connecté entre une seconde borne du premier transistor et une seconde borne du troisième transistor. Ce circuit de commande à courant de décharge comprend de préférence une résistance de décharge et une rétroaction par transistor à courant miroir commandée par un condensateur de sortie.
EP03759287A 2002-09-18 2003-09-16 Tampon de sortie a commande rapide Withdrawn EP1559196A4 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
ITAO20020811 2002-09-18
ITAO20020811 2002-09-18
US323614 2002-12-18
US10/323,614 US6734701B2 (en) 2002-09-18 2002-12-18 Fast controlled output buffer
PCT/US2003/029307 WO2004027777A2 (fr) 2002-09-18 2003-09-16 Tampon de sortie a commande rapide

Publications (2)

Publication Number Publication Date
EP1559196A2 true EP1559196A2 (fr) 2005-08-03
EP1559196A4 EP1559196A4 (fr) 2009-07-01

Family

ID=56290486

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03759287A Withdrawn EP1559196A4 (fr) 2002-09-18 2003-09-16 Tampon de sortie a commande rapide

Country Status (3)

Country Link
EP (1) EP1559196A4 (fr)
KR (1) KR20050049496A (fr)
NO (1) NO20051557L (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3929350C1 (en) * 1989-09-04 1990-07-19 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De CMOS input to digital output signal level converter - has PMOS and NMOS FET control transistors and current limiter
JPH03121618A (ja) * 1989-10-04 1991-05-23 Toshiba Corp 出力回路
US5367210A (en) * 1992-02-12 1994-11-22 Lipp Robert J Output buffer with reduced noise
US5214320A (en) * 1992-06-12 1993-05-25 Smos Systems, Inc. System and method for reducing ground bounce in integrated circuit output buffers
US5703517A (en) * 1993-05-25 1997-12-30 Texas Insturments Incorporated Power reduction in a temperature compensating transistor circuit
DE19829487C1 (de) * 1998-07-01 1999-09-23 Siemens Ag Ausgangstreiber eines integrierten Halbleiterchips

Also Published As

Publication number Publication date
KR20050049496A (ko) 2005-05-25
NO20051557L (no) 2005-03-23
EP1559196A4 (fr) 2009-07-01

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