EP1609171A2 - Support de plaquettes presentant des caracteristiques de traitement ameliorees - Google Patents

Support de plaquettes presentant des caracteristiques de traitement ameliorees

Info

Publication number
EP1609171A2
EP1609171A2 EP04718089A EP04718089A EP1609171A2 EP 1609171 A2 EP1609171 A2 EP 1609171A2 EP 04718089 A EP04718089 A EP 04718089A EP 04718089 A EP04718089 A EP 04718089A EP 1609171 A2 EP1609171 A2 EP 1609171A2
Authority
EP
European Patent Office
Prior art keywords
wafer carrier
wafers
slot
wafer
radius
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04718089A
Other languages
German (de)
English (en)
Inventor
Richard F. Buckley
Andrew G. Haerle
Han C. Science-Based Industrial Park Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Saint Gobain Ceramics and Plastics Inc
Original Assignee
Saint Gobain Ceramics and Plastics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Saint Gobain Ceramics and Plastics Inc filed Critical Saint Gobain Ceramics and Plastics Inc
Publication of EP1609171A2 publication Critical patent/EP1609171A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/10—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
    • H10P72/15—Horizontal carrier comprising wall type elements whereby the substrates are vertically supported, e.g. comprising sidewalls

Definitions

  • the present invention relates generally to kiln furniture, and more specifically, to a wafer carrier for supporting wafers to undergo processing such as exposure to a high temperature processing operation, hi addition, the present invention generally relates to processing wafers utilizing such a wafer carrier.
  • semiconductor processes typically employ workpieces to support and or transport semiconductor wafers during various processing steps, including high temperature processes which include annealing, chemical vapor deposition, oxidation, and others.
  • horizontal and vertical wafer carriers also known in the art as wafer boats, are utilized to support a plurality of wafers, typically spaced apart from each other at a constant pitch forming an array of wafers.
  • exposure of the wafer to processing operations is generally known as "batch processing," in which a plurality of wafers are processed simultaneously.
  • device fabrication sometimes utilizes an extended oxidation step, in which the semiconductor wafers are oxidized, sometimes for extended periods of time beyond what would normally be encountered in conventional semiconductor processing. For example, it is not uncommon to expose a wafer to a processing operation for days at a time, such as on the order of five to ten days. As noted above, oftentimes such a processing operation includes oxidation of the wafers.
  • the present inventors have encountered defects in the wafers after being subjected to such processing operations, such as localized or even catastrophic fracture of the wafers. Other defects include deformation and notching of the wafers around the outer periphery, particularly at those points contacting the wafer carrier such as the bottom support portion of the wafer carrier in the case of a horizontal wafer boat.
  • a wafer carrier for supporting a plurality of wafers, the carrier including a plurality of slots provided in a cradle, the cradle comprising silicon carbide and having an oxide layer overlying the silicon carbide.
  • a wafer carrier is provided for supporting a plurality of wafers, the carrier including a plurality of slots provided in a cradle, the cradle comprising silicon carbide and having an oxide layer overlying the silicon carbide.
  • a wafer carrier is provided having a plurality of slots having a particular width. In particular, a portion of each slot has a width (w s ), wherein w s is not less than 1.30 t w and t w is a thickness of the wafers.
  • a wafer carrier for supporting a plurality of wafers, the wafers having a radius r w , and the wafer carrier including a plurality of slots for supporting the wafers, wherein at least a portion of each slot has a radius of curvature r s , which is not less than about 1.15 r w .
  • r s may have a negative value while r w has a positive value.
  • methods are provided for processing a plurality of wafers, in which a plurality of wafers are loaded onto a wafer carrier having any one of or all the features described above, and subjecting the wafers to a processing operation as-loaded on the wafer carrier.
  • the processing operation may be one in which the wafers are exposed to an oxidizing environment to oxidize the wafers.
  • FIG. 1 is a perspective view of a horizontal wafer carrier according to an embodiment of the present invention.
  • FIG. 2 is a sectional view of a horizontal wafer carrier according to an embodiment of the present invention, loaded with a silicon wafer.
  • FIG. 3 is a graph illustrating the growth curve of oxide on a silicon carbide wafer carrier.
  • FIG. 4 represents the radius of curvature of a slot loaded with a semiconductor wafer according to an embodiment of the present invention.
  • FIG. 5 represents the radius of curvature of a slot loaded with a semiconductor wafer according to another embodiment of the present invention.
  • FIG. 6 represents the radius of curvature of a slot loaded with a semiconductor wafer according to yet another embodiment of the present invention.
  • FIG. 7 represents thickness of the wafer in cross-section as loaded in a slot, relative to width of slot, according to an embodiment of the present invention.
  • a particular wafer carrier is provided for supporting a plurality of wafers.
  • FIG. 1 illustrating a perspective view of a wafer carrier according to an embodiment of the present invention.
  • wafer carrier 1 includes a cradle 2 having a generally open structure and including a plurality of cradle arms 3 which take on a generally arcuate shape, and which are integrated with a plurality of support members for supporting the wafers.
  • first, second, and third support members, 10, 12 and 14 are provided, each of which protrudes radially inward, and along which a plurality of slots 16 are provided.
  • Each slot 16 is disposed and oriented so as to be positioned along the same arc of fixed radius, to support a single respective wafer.
  • Each slot is made up of first, second and third slot segments 18, 20 and 22, respectively, each of which respectively being positioned along first, second and third support members 10, 12, and 14.
  • FIG. 2 a cross-sectional view is provided illustrating the orientation of wafer 30 as engaged and loaded onto the wafer carrier 1.
  • the general orientation of the wafer carrier illustrated in FIGs. 1 and 2 is horizontal, and is the orientation of the wafer carrier in use, particularly, in a semiconductor fab environment.
  • the carrier supports the wafers in a generally upright, vertical position.
  • the slots 16 are arranged in a linear array and spaced apart from each other at a constant pitch.
  • second slot segments 20 are shown to be spaced apart from each other at a constant pitch, and in an array format.
  • the wafers are held by the carrier linearly, forming a horizontal stack of wafers.
  • the pitch of the grooves, and accordingly, the pitch of the wafers may vary depending on the particular application, but generally lies within a range of about 2 to about 4 mm, nominally about 2.38mm.
  • the first, second and third support members 10, 12 and 14 are positioned along an arc 32 which has a radius equal to a radius of the wafer r w , such that the first, second and third support members are positioned sequentially along the arc 32 and the second support member is positioned circumferentially between the first and third support members 10, 14.
  • the second support member generally supports a larger portion of the weight of the wafer, since it is disposed at a bottom-most position, i.e., at the six o'clock position.
  • the arc 32 sweeps an angle which is not greater than 180 degrees, so as to facilitate loading of the wafers.
  • the support portions are positioned to define an arc 32 which is not greater than about 150 degrees, or typically not greater than about 130 degrees.
  • the wafer carrier may have a different number of support members.
  • the second support member may be bifurcated so as to form two distinct support members which have distinct slot segments.
  • the support members may be equally spaced apart from the bottom-most six o'clock position.
  • the wafer carrier has a generally open design, which provides several advantages as described in more detail below.
  • the windows defined between the cradle arms 3 and the support members provide at least 40% open area along an outer partial-cylindrical surface of the cradle.
  • the open area is not less than about 50%.
  • This open design of the wafer carrier advantageously improves gas flow around the wafer carrier during the pre-oxidation step, to form a conformal, relatively uniform oxide layer/ [1026]
  • the cradle is comprised of silicon carbide.
  • the silicon carbide comprises recrystallized silicon carbide, which is a material understood in the art.
  • a green body containing semiconductor-grade silicon carbide powder is mixed with sintering aids and binders, molded into a desired shaped, dried, heated to burn-out organic binders, and heat treated to densify and recrystallize the body. Following densification, machining steps may be used to arrive at the final dimensions of the wafer carrier.
  • silicon carbide substrate may be formed by a conversion process, in which a carbon preform is converted by gas phase or liquid-phase techniques into silicon carbide.
  • the preform is formed of a carbonaceous material, such as semiconductor-grade graphite.
  • the carrier may be impregnated with silicon.
  • Such a compositional feature is known as Si-SiC or siliconized silicon carbide.
  • the substrate is impregnated with molten silicon, to densify the structure to an extent suitable for use in refractory applications such as in the semiconductor processing environment.
  • the siliconized silicon carbide may be coated with a further layer of silicon carbide, such as chemical vapor deposited (CVD) silicon carbide.
  • the wafer carrier may be formed of free-standing SiC formed by CVD. h this case, an extended CVD process is carried out to form the wafer carrier itself.
  • An oxide layer is provided so as to overlie the silicon carbide of the wafer carrier.
  • the oxide layer may be formed by oxidation of the carrier in an oxidizing environment, such as by oxidizing the carrier in an oxygen containing environment at an elevated temperature, such as within a range of 950 to about 1300 degrees C, and more generally in a range of about 1000 to about 1250 degrees C.
  • Oxidation may be carried out in a dry or wet atmosphere, and is typically carried out at atmospheric pressure.
  • a wet ambient can be generated by introducing steam, and functions to increase the rate of oxidation and improve density of the oxide layer.
  • wet oxidation at 1150 °C may form a robust, thick (such as about 2-3 microns) oxide layer on the of about 12- 48 hours.
  • a robust, thick oxide layer may take on the order of 5 days, such as 10-20 days for form according to a dry oxidation treatment.
  • the oxide layer is formed by oxidation, it may also be deposited, such as by reacting TEOS source gas.
  • thermally grown layers may be preferred.
  • the oxide layer is silicon oxide, generally SiO 2 .
  • the silicon oxide layer may be in direct contact with the silicon carbide of the wafer carrier.
  • an intermediate layer, such as silicon may be present between the silicon carbide and the overlying oxide layer, as in the case of silicon-impregnated silicon carbide.
  • FIG. 3 illustrates the growth curve of an oxide layer as a function of time on the silicon carbide wafer carrier.
  • the oxide layer follows a generally parabolic growth curve.
  • the oxide layer has a thickness which is above the relatively rapid growth portion of the curve.
  • the oxide layer may have a thickness greater than about 0.5 microns, or particularly greater than about 0.75 microns, such as greater than about 1.0 microns, and even 1.5 microns.
  • the oxide has a thickness or at least 2 microns, such as on the order of about 2 to about 3 microns.
  • the oxide layer according embodiments of the present invention is a layer which is provided on the wafer carrier, as opposed to any native oxide which may be present on the wafer carrier, but in relatively low thicknesses.
  • the oxide layer described above is generally formed by thermal oxidation techniques, other techniques may also be utilized, such as direct deposition of an oxide layer.
  • the wafers may catastrophically fail by a cracking mechanism.
  • a pre-oxidation step to form an oxide layer on the carrier, growth of an oxide layer on the carrier during thermal processing of the wafers is attenuated, and the propensity of bonding between the wafers and the carrier is reduced, thereby enhancing process control and wafer yield.
  • the slots in the wafer carrier have a particular radius of curvature r s that further enhances process control and wafer yield, particularly during high temperature processing as described above.
  • the wafer has a nominal radius r w.
  • Current state of the art wafer fabs utilize 8 inch, and increasingly 12 inch (300mm diameter) wafers. Accordingly, newer fabs may employ wafers having a radius r w which is on the order of about 150 mm, although older fabs may utilize smaller wafers and newer generation fabs larger.
  • the radius of curvature r s of the slot is not less then about 1.15 r w .
  • the radius curvature of the slot for supporting the wafer is larger than the radius of the wafers by at least 15%.
  • r s is not less than about 1.25 r w> such as 1.35 r w> and 1.50 r w .
  • r s is shown to be approximately twice that of r w .
  • the radius of curvature of the slot may have the opposite orientation, that is, have a negative radius of curvature as compared with the radius r w of the wafer. This is shown in FIG. 6, in which the slot has a generally convex shape and has a radius which extends in a direction opposite of the radius of the wafer, from the point of contact between the wafer and the slot.
  • each slot segment has the same radius of curvature.
  • typically at least a portion of the second slot segment along the second support member has a radius characteristic as described above.
  • the potential oxidation bond area between the wafer and the carrier is minimized.
  • the minimized bonding interface is weaker and more likely to break during processing (e.g., during cooling) thereby attenuating thermal stresses in the wafer which can cause fracture as described above.
  • the slots of the wafer carrier has a width w s which is greater than a thickness t w of the wafers.
  • the width w s is generally not less than about 1.30 t w .
  • w s is not less than about 1.35 t w , and may be within a range of about 1.35 t w to about 1.50 t w .
  • FIG. 7 illustrates the width of the slot w s , with respect to the thickness of the wafer t w (not shown to scale).
  • the actual thickness t w of the wafers may vary based upon wafer brand, intended use, wafer diameter, composition (e.g., silicon on insulator (SOI)), etc.
  • wafers typically have a thickness within a range of about 0.45 mm to about 0.80 mm, more typically between about 0.50 to about 0.765 mm.
  • constraint of the wafer within the slot tends to cause the wafer to creep at high temperatures, causing notching.
  • the formation of notches in the wafer around the outer periphery tends to form a mechanical interlocking structure, which is disadvantageous.
  • the notch tends to engage the slot and is responsible for placing mechanical stresses in the wafer upon cooling due to differential thermal contraction characteristics of the wafer and the wafer carrier.
  • the present invention also provides for processing for a plurality of wafers, known as batch processing.
  • a wafer carrier is loaded with a plurality of wafers, generally arranged in a linear array at a constant pitch. Thereafter, the wafer/wafer carrier assembly is placed in a furnace, such as a process tube, for high temperature processing.
  • a furnace such as a process tube
  • one desirable processing operation is the formation of a relatively thick oxide layer on the wafers, particularly suitable for MEMS and opto-electronic applications.

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packaging Frangible Articles (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

L'invention concerne un support de plaquettes destiné à supporter une pluralité de plaquettes, lequel support présente une pluralité de rainures formées dans un berceau, ce berceau étant constitué de carbure de silicium recouvert d'une couche d'oxyde.
EP04718089A 2003-03-28 2004-03-05 Support de plaquettes presentant des caracteristiques de traitement ameliorees Withdrawn EP1609171A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US402915 2003-03-28
US10/402,915 US20040188319A1 (en) 2003-03-28 2003-03-28 Wafer carrier having improved processing characteristics
PCT/US2004/006847 WO2004095545A2 (fr) 2003-03-28 2004-03-05 Support de plaquettes presentant des caracteristiques de traitement ameliorees

Publications (1)

Publication Number Publication Date
EP1609171A2 true EP1609171A2 (fr) 2005-12-28

Family

ID=32989844

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04718089A Withdrawn EP1609171A2 (fr) 2003-03-28 2004-03-05 Support de plaquettes presentant des caracteristiques de traitement ameliorees

Country Status (7)

Country Link
US (1) US20040188319A1 (fr)
EP (1) EP1609171A2 (fr)
JP (2) JP2006521689A (fr)
KR (1) KR100755196B1 (fr)
CN (1) CN100390927C (fr)
TW (1) TWI288454B (fr)
WO (1) WO2004095545A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2006112052A1 (ja) * 2005-03-30 2008-11-27 イビデン株式会社 炭化珪素含有粒子、炭化珪素質焼結体を製造する方法、炭化珪素質焼結体、及びフィルター
CN101928934B (zh) * 2009-06-18 2012-11-28 中芯国际集成电路制造(上海)有限公司 提高晶圆的高温氧化物层均匀性的方法
CN103151289B (zh) * 2011-12-07 2015-11-25 无锡华润华晶微电子有限公司 晶舟、晶舟转移装置以及包括其的晶片转移系统
JP5991284B2 (ja) * 2013-08-23 2016-09-14 信越半導体株式会社 シリコンウェーハの熱処理方法
CN103681416A (zh) * 2013-11-29 2014-03-26 上海华力微电子有限公司 一种监控多晶硅炉管晶圆厚度的方法
CN104269351B (zh) * 2014-09-30 2017-02-22 上海华力微电子有限公司 改善hcd氮化硅沉积工艺的应力缺陷的方法
US20180119278A1 (en) * 2015-04-13 2018-05-03 Kornmeyer Carbon-Group Gmbh Pecvd boat
JP7251458B2 (ja) * 2019-12-05 2023-04-04 株式会社Sumco シリコンウェーハの製造方法

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3634116A (en) * 1969-06-02 1972-01-11 Dow Corning Silicon-carbide-encased graphite articles and their production
NL7206014A (fr) * 1971-07-07 1973-01-09
US3923156A (en) * 1974-04-29 1975-12-02 Fluoroware Inc Wafer basket
JPS512161U (fr) * 1974-06-24 1976-01-09
JPS5285476A (en) * 1976-01-09 1977-07-15 Hitachi Ltd Semiconductor wafer accommodating jig
US4355974A (en) * 1980-11-24 1982-10-26 Asq Boats, Inc. Wafer boat
JPS59191327A (ja) * 1983-04-15 1984-10-30 Hitachi Ltd 熱処理用治具
US4548159A (en) * 1984-07-06 1985-10-22 Anicon, Inc. Chemical vapor deposition wafer boat
JPS6142153A (ja) * 1984-08-03 1986-02-28 Fujitsu Ltd 耐熱治具
JPS61213374A (ja) * 1985-03-18 1986-09-22 Hitachi Micro Comput Eng Ltd 治具
US4653636A (en) * 1985-05-14 1987-03-31 Microglass, Inc. Wafer carrier and method
JPH0622262B2 (ja) * 1985-07-01 1994-03-23 東芝セラミツクス株式会社 半導体ウェハ支持用ボートの製造方法
JP2573480B2 (ja) * 1985-11-22 1997-01-22 東芝セラミックス 株式会社 半導体熱処理用治具
JPH0824140B2 (ja) * 1986-12-26 1996-03-06 東芝セラミックス株式会社 シリコンウエ−ハ処理用治具
JP2548949B2 (ja) * 1987-09-01 1996-10-30 東芝セラミックス株式会社 半導体製造用構成部材
JPH0752720B2 (ja) * 1988-05-31 1995-06-05 信越半導体株式会社 半導体ウェーハ保持装置の保持溝形成方法
US4981222A (en) * 1988-08-24 1991-01-01 Asq Boats, Inc. Wafer boat
JPH04287915A (ja) * 1991-02-07 1992-10-13 Mitsubishi Electric Corp ウェハーボート
JPH065530A (ja) * 1992-06-17 1994-01-14 Toshiba Corp 熱処理炉ボート
JPH06302532A (ja) * 1993-04-13 1994-10-28 Japan Energy Corp 化合物半導体単結晶ウェハの熱処理方法及びそれに用いるウェハ支持具
US5417767A (en) * 1993-12-28 1995-05-23 Stinson; Mark G. Wafer carrier
US5538230A (en) * 1994-08-08 1996-07-23 Sibley; Thomas Silicon carbide carrier for wafer processing
JP3285723B2 (ja) * 1994-11-17 2002-05-27 信越半導体株式会社 半導体熱処理用治具及びその表面処理方法
US5443649A (en) * 1994-11-22 1995-08-22 Sibley; Thomas Silicon carbide carrier for wafer processing in vertical furnaces
US5702997A (en) * 1996-10-04 1997-12-30 Saint-Gobain/Norton Industrial Ceramics Corp. Process for making crack-free silicon carbide diffusion components
JPH10242254A (ja) * 1997-02-21 1998-09-11 Ado Matsupu:Kk 半導体製造用治具
JP3362113B2 (ja) * 1997-07-15 2003-01-07 日本碍子株式会社 耐蝕性部材、ウエハー設置部材および耐蝕性部材の製造方法
US6171400B1 (en) * 1998-10-02 2001-01-09 Union Oil Company Of California Vertical semiconductor wafer carrier
US6162543A (en) * 1998-12-11 2000-12-19 Saint-Gobain Industrial Ceramics, Inc. High purity siliconized silicon carbide having high thermal shock resistance
US20030196588A1 (en) * 2000-02-10 2003-10-23 Norihiro Kobayashi Silicon boat with protective film, method of manufacture thereof, and silicon wafer heat-treated using silicon boat
US6699401B1 (en) * 2000-02-15 2004-03-02 Toshiba Ceramics Co., Ltd. Method for manufacturing Si-SiC member for semiconductor heat treatment
US7055702B1 (en) * 2000-06-06 2006-06-06 Saint-Gobain Ceramics & Plastics, Inc. Slip resistant horizontal semiconductor wafer boat
US6488497B1 (en) * 2001-07-12 2002-12-03 Saint-Gobain Ceramics & Plastics, Inc. Wafer boat with arcuate wafer support arms
JP3535853B2 (ja) * 2001-09-18 2004-06-07 エム・エフエスアイ株式会社 基板の支持固定具、及びこれを用いた基板表面の乾燥方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004095545A3 *

Also Published As

Publication number Publication date
WO2004095545A2 (fr) 2004-11-04
CN100390927C (zh) 2008-05-28
KR20060002875A (ko) 2006-01-09
WO2004095545A3 (fr) 2005-05-12
HK1089561A1 (zh) 2006-12-01
JP2006521689A (ja) 2006-09-21
WO2004095545A8 (fr) 2005-12-08
US20040188319A1 (en) 2004-09-30
KR100755196B1 (ko) 2007-09-05
TW200425384A (en) 2004-11-16
TWI288454B (en) 2007-10-11
CN1765005A (zh) 2006-04-26
JP2010103554A (ja) 2010-05-06

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