EP1620880A4 - Halbleitersubstrat und verfahren zu seiner herstellung - Google Patents

Halbleitersubstrat und verfahren zu seiner herstellung

Info

Publication number
EP1620880A4
EP1620880A4 EP04730068A EP04730068A EP1620880A4 EP 1620880 A4 EP1620880 A4 EP 1620880A4 EP 04730068 A EP04730068 A EP 04730068A EP 04730068 A EP04730068 A EP 04730068A EP 1620880 A4 EP1620880 A4 EP 1620880A4
Authority
EP
European Patent Office
Prior art keywords
manufacturing
semiconductor substrate
method therefor
therefor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04730068A
Other languages
English (en)
French (fr)
Other versions
EP1620880A1 (de
Inventor
Takao Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP1620880A1 publication Critical patent/EP1620880A1/de
Publication of EP1620880A4 publication Critical patent/EP1620880A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
EP04730068A 2003-05-07 2004-04-28 Halbleitersubstrat und verfahren zu seiner herstellung Withdrawn EP1620880A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003128917A JP4532846B2 (ja) 2003-05-07 2003-05-07 半導体基板の製造方法
PCT/JP2004/006178 WO2004100233A1 (en) 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor

Publications (2)

Publication Number Publication Date
EP1620880A1 EP1620880A1 (de) 2006-02-01
EP1620880A4 true EP1620880A4 (de) 2008-08-06

Family

ID=33432059

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04730068A Withdrawn EP1620880A4 (de) 2003-05-07 2004-04-28 Halbleitersubstrat und verfahren zu seiner herstellung

Country Status (6)

Country Link
EP (1) EP1620880A4 (de)
JP (1) JP4532846B2 (de)
KR (1) KR100725141B1 (de)
CN (2) CN100358104C (de)
TW (1) TWI259514B (de)
WO (1) WO2004100233A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5128781B2 (ja) * 2006-03-13 2013-01-23 信越化学工業株式会社 光電変換素子用基板の製造方法
CN108231695A (zh) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 复合衬底及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (de) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha Ein durch Verkleben hergestelltes SOI Substrat
EP0994503A1 (de) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Struktur mit einer dünnen Schicht aus einem aus elektrisch leitfähigen und isolierenden Zonen zusammengesetztem Material und zugehöriges Herstellungsverfahren
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794409A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd Ｉｉｉ−ｖ族化合物半導体薄膜の形成方法
JP3879173B2 (ja) * 1996-03-25 2007-02-07 住友電気工業株式会社 化合物半導体気相成長方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (de) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha Ein durch Verkleben hergestelltes SOI Substrat
EP0994503A1 (de) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Struktur mit einer dünnen Schicht aus einem aus elektrisch leitfähigen und isolierenden Zonen zusammengesetztem Material und zugehöriges Herstellungsverfahren
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2004100233A1 *
VENKATASUBRAMANIAN R: "HIGH-QUALITY EUTECTIC-METAL-BONDED ALGAAS-GAAS THIN FILMS ON SI SUBSTRATES", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, vol. 60, no. 7, 17 February 1992 (1992-02-17), pages 886 - 888, XP000290448, ISSN: 0003-6951 *

Also Published As

Publication number Publication date
CN100358104C (zh) 2007-12-26
JP4532846B2 (ja) 2010-08-25
JP2004335693A (ja) 2004-11-25
WO2004100233A1 (en) 2004-11-18
KR20060005406A (ko) 2006-01-17
KR100725141B1 (ko) 2007-06-07
CN101145509A (zh) 2008-03-19
CN1698180A (zh) 2005-11-16
TWI259514B (en) 2006-08-01
TW200425261A (en) 2004-11-16
EP1620880A1 (de) 2006-02-01

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Legal Events

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