Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
  • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

• the present invention relates to a semiconductor substrate and a manufacturing method therefor and, more particularly, to a semiconductor substrate which has a gallium arsenide layer and a manufacturing method therefor.
• a device on a compound semiconductor substrate made of gallium arsenide and other materials has for example high performance, high speed and good light-emitting properties.
• the compound semiconductor substrate is expensive and has low mechanical strength, and is difficult to manufacture a large-area substrate. Under these circumstances, attempts have been made to heteroepitaxially grow a compound semiconductor on a silicon substrate which is inexpensive, has a high mechanical strength, and can form a large-area substrate.
• 3,257,624 discloses a method of obtaining a large-area semiconductor substrate by heteroepitaxially growing a compound semiconductor layer on a silicon substrate, implanting ions in the silicon substrate, bonding the silicon substrate to another substrate, heating the ion-implanted layer and causing it to collapse, and dividing the bonded substrate stack.
• Such a method needs to relax mismatch between the lattice constant of silicon and that of the compound semiconductor to obtain good crystallinity, depending on the specifications of a required compound semiconductor substrate.
• 2,877,800 discloses a method of obtaining a compound semiconductor substrate by growing a compound semiconductor layer on a porous silicon layer formed on a silicon substrate, bonding the silicon substrate to another substrate, cutting the porous silicon layer with a jet of a fluid, and dividing the bonded substrate stack.
• the porous silicon layer between the silicon and the compound semiconductor relaxes mismatch between the lattice constant of silicon and that of the compound semiconductor to some degree to form a heteroepitaxial layer. It is difficult to eliminate the mismatch between the lattice constant of the porous silicon and that of the compound semiconductor, and thus the resultant compound semiconductor may have poor crystallinity.
• the specifications of some required compound semiconductor devices may limit the range of applications of a compound semiconductor substrate formed by such a manu acturing method, and the compound semiconductor devices may not sufficiently exhibit their superiority.
• the present invention has been made on the basis of the above-mentioned consideration, and has as its object to provide a method of manufacturing a semiconductor substrate which sufficiently exhibits its superiority as a compound semiconductor device and can ensure good economy.
• a semiconductor substrate manufacturing method characterized by comprising a first step of implanting ions in a first substrate which has a gallium arsenide layer on a germanium member and forming an ion-implanted layer in the first substrate, a second step of bonding the first substrate to a second substrate to form a bonded substrate stack, and a third step of dividing the bonded substrate stack at the io -implanted layer.
• the gallium arsenide layer is preferably formed by epitaxial growth.
• the first step may comprise a step of forming a compound semiconductor layer on the gallium arsenide layer.
• the ions preferably include one of hydrogen ions and ions of a rare gas.
• the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by annealing the bonded substrate stack.
• the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by a jet of a fluid or a static pressure.
• the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by inserting a member in the ion-implanted layer.
• the manufacturing method preferably further comprises a step of removing a part of the ion-implanted layer left on a part of the gallium arsenide layer, which has been transferred to the second substrate after the third step.
• the manufacturing method preferably further comprises a step of planarizing a surface of the germanium member obtained by division in the division step and reusing the germanium member in the first step.
• Fig. 1 is a view for explaining a semiconductor substrate manufacturing method according to a preferred embodiment of the present invention
• Fig. 2 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention.
• Fig. 3 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention
• Fig. 4 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention
• Fig. 5 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention
• Fig. 6 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention.
• Fig. 7 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention.
• Figs. 1 to 7 are views for explaining a substrate manufacturing method according to the preferred embodiment of the present invention.
• a germanium member 11 is prepared.
• a gallium arsenide layer 12 is formed on the surface of the germanium member 11 by epitaxial growth. Since mismatch between the lattice constant of germanium and that of gallium arsenide is small, a gallium arsenide layer with good crystallinity can be formed on the germanium member 11. Epitaxial growth allows the gallium arsenide layer to have a uniform thickness.
• hydrogen ions are implanted in the surface of the gallium arsenide layer 12 shown in Fig. 2.
• An ion-implanted layer 13 is formed in the gallium arsenide layer 12, thereby forming a first substrate 10.
• ions of a rare gas such as helium, neon, argon, krypton, xenon, or the like may be used alone or in combination in the implantation.
• an insulating layer is formed on the surface of the gallium arsenide layer 12, prior to the ion implantation.
• the ion-implanted layer 13 can be formed in at least one of the germanium member 11 and the gallium arsenide layer 12.
• a second substrate 20 is bonded to the surface of the first substrate 10 to form a bonded substrate stack 30.
• a silicon substrate or a substrate obtained by forming an insulating layer such as an Si0 2 layer on its surface can be adopted as the second substrate 20.
• any other substrate such as an insulating substrate (e.g., a glass substrate) may be used as the second substrate 20.
• the bonded substrate stack 30 is divided at the ion-implanted layer 13 into two substrates.
• the ion-implanted layer 13 has highly concentrated microcavities , microbubbles , distortions, or defects, and is more fragile than the remaining portion of the bonded substrate stack 30.
• This division can be performed by, for example, annealing the bonded substrate stack 30.
• the division can be performed by, for example, a method of using a fluid.
• a method of forming a jet of a fluid (liquid or gas) and injecting the jet to the separation layer 12, a method which utilizes the static pressure of a fluid, or the like may preferably be used.
• a method using water as the fluid is called a water jet method.
• the division can be performed by inserting a solid member such as a wedge into the separation layer 12.
• an ion-implanted layer 13b left on a gallium arsenide layer 12b of the second substrate 20 is removed using an etchant or the like.
• the gallium arsenide layer 12b is preferably be used as an etching stopper layer.
• a hydrogen annealing step, polishing step, or the like may be performed as needed to planarize the second substrate.
• a semiconductor substrate 40 shown in Fig. 7 is obtained.
• the semiconductor substrate 40 shown in Fig. 7 has the thin gallium arsenide layer 12b on its surface.
• the expression "thin gallium arsenide layer” is intended to mean a layer thinner than a general semiconductor substrate.
• the thickness of the gallium arsenide layer 12b preferably falls within a range of 5 nm to 5 Aim.
• Another compound semiconductor layer of AlGaAs, GaP, InP, InAs , or the like can be formed on the gallium arsenide layer 12b, depending on the specifications of the semiconductor device.
• an ion-implanted layer 13a or the like left on the germanium member 11 is removed using an etchant or the like. Then, the hydrogen annealing step, polishing step, or the like may be performed to planarize the surface of the germanium member.
• the planarized substrate can be reused as the germanium member 11 to be used in the step shown in Fig. 1. Repeated reuse of the germanium member 11 can greatly reduce the manufacturing cost of a semiconductor substrate.
• the manufacturing method according to the present invention makes it possible to obtain a semiconductor substrate which has a gallium arsenide layer with a uniform thickness and good crystallinity. Also, the manufacturing method according to the present invention can greatly reduce the manufacturing cost of a semiconductor substrate with a gallium arsenide layer. Therefore, according to the present invention, there can be provided a method of manufacturing a semiconductor substrate which sufficiently exhibits its superiority as a compound semiconductor device and can ensure good economy.

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• Recrystallisation Techniques (AREA)
• Element Separation (AREA)

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• 2003
  • 2003-05-07 JP JP2003128917A patent/JP4532846B2/ja not_active Expired - Fee Related
• 2004
  • 2004-04-27 TW TW093111750A patent/TWI259514B/zh not_active IP Right Cessation
  • 2004-04-28 EP EP04730068A patent/EP1620880A4/de not_active Withdrawn
  • 2004-04-28 WO PCT/JP2004/006178 patent/WO2004100233A1/en not_active Ceased
  • 2004-04-28 KR KR1020057020457A patent/KR100725141B1/ko not_active Expired - Fee Related
  • 2004-04-28 CN CNB2004800006869A patent/CN100358104C/zh not_active Expired - Fee Related
  • 2004-04-28 CN CNA2007101812355A patent/CN101145509A/zh active Pending

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