Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
  • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors incorporating printed capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/0239—Signal transmission by AC coupling
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
  • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
  • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
  • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
  • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
  • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/096—Vertically aligned vias, holes or stacked vias
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09672—Superposed layout, i.e. in different planes

Definitions

• the present invention relates to a method for manufacturing embedded capacitors .
• the method can include the steps of forming at least one bore in a dielectric substrate.
• the dielectric substrate can be mechanically punched or laser cut to form the bore.
• the bore can be filled with a conductive material to form a first electrode.
• a conductor can be formed on the dielectric substrate, the conductor not being electrically continuous with the first electrode.
• a depth and/or cross sectional area of the bore can be selected to provide a desired amount of capacitive coupling between the electrode and the conductor.
• the method for manufacturing embedded capacitors also can include the steps of forming at least one bore in a first dielectric layer and filling the bore with a conductive material.
• a first conductor can be disposed on the first dielectric layer, the first conductor being in electrical contact with the first electrode.
• a second conductor can be disposed on a second dielectric substrate.
• the first and second dielectric layers can be joined such that the first and second conductors are not electrically continuous.
• the dimensions of the first conductor and/or the second conductor can be selected to provide a desired amount of capacitive coupling between the first conductor and the second conductor.
• the present invention also relates to an embedded capacitor which can include a substrate having an electrode.
• the electrode can include a conductive material which has been filled into a bore within the substrate.
• the first and second bores can be electrically connected.
• the present invention also relates to an embedded capacitor which includes a substrate having a plurality of dielectric layers.
• An electrode can be disposed in a first of the dielectric layers, the electrode including a conductive material which has been filled into a bore within the substrate.
• a first conductor can be disposed on the dielectric layer, the first conductor being in electrical contact with the electrode.
• a second conductor can be disposed on a second of the dielectric layers, the second conductor not being electrically continuous with the electrode. Dimensions of the first and second conductors can be selected to provide a desired amount of capacitive coupling between the first and second conductors.
• the amount of dielectric material disposed between the electrode and the other conductor can be controlled by selecting the depth of the electrode within the substrate.
• the electrode can extend through a single dielectric layer, or a plurality of dielectric layers.
• the electrodes formed within the vias can be manufactured with much higher tolerances than other types of electrodes. Higher manufacturing tolerances can be maintained because the cross sectional area and the depth of the vias can be accurately controlled.
• the cross sectional area of the vias can be accurately controlled by using a high accuracy mechanical punching system or a laser cutting system.
• the depth of the vias can be accurately controlled by the use of dielectric layers having precise thicknesses. Hence, costly processes, such as laser trimming, can be avoided.
• Such processes are sometimes used to adjust the size of the electrodes in order to tune capacitance values. Accordingly, forming electrodes using conductor filled vias results in a capacitor that can be manufactured more economically and with better quality than other types of low tolerance capacitors . Moreover, the ability to tightly control electrode tolerances facilitates the use of dielectric layers having a very high relative permittivity. In consequence, embedded capacitors which have a wide range of capacitance values can be provided within a single substrate. For example, the dielectric layers can be provided with a relative permittivity ( ⁇ r ) from less than 6 to greater than 2400, and capacitors can be provided within the substrate that have values ranging from less than 20 pF to more than 220 nF. Referring to Fig.
• the substrate 100 can include one or more layers, for example layers 110, 120, 130, 140. Typical layer thicknesses can be from 0.5 mils to 10 mils.
• the substrate layers 110, 120, 130, 140 can be formed from any dielectric material wherein vias can be formed.
• the substrate layers can be formed from ceramic material, such as low temperature co-fired ceramic (LTCC) or high temperature co-fired ceramic (HTCC) .
• the substrate layers also can be formed from fiberglass or epoxy insulator reinforced with fiber, such as FR4.
• polymers, such as polymide, polyester, polypropylene or other polymer film can be used as the dielectric.
• a conventional thick film screen printing process can be used to deposit conductive layers on the substrate layers and the substrate layers can be baked to dry the conductive layers.
• the substrate layers 110, 120, 130, 140 can be joined to form substrate 400, as shown in Fig. 4.
• additional substrate layers also can be joined to substrate layers 110, 120, 130, 140.
• the additional substrate layers also can comprise vias and conductive layers.
• conductor filled vias in the substrate layers 110, 120, 130, 140 which are opposingly disposed can be aligned to form electrodes 465, electrodes 467 and electrodes 475, each of which can extend through multiple substrate layers.
• the layers can be laminated together using a variety of lamination methods.
• the substrate layers can be stacked and hydraulically pressed with heated platens.
• a uniaxial lamination method can press the ceramic substrate layers together at 3000 psi for 10 minutes using plates heated to 70° C.
• the ceramic substrate layers can be rotated 180° following the first 5 minutes.
• the ceramic substrate layers can be vacuum sealed in a plastic bag and then pressed using heated water.
• the time, temperature and pressure can be the same as those used in the uniaxial lamination process; however, rotation after 5 minutes is not required.
• the structure can be fired inside a kiln on a flat tile.
• the ceramic substrate layers can be baked between 200° C and 500° C for one hour and a peak temperature between 850° and 900° can be applied for greater than 15 minutes.
• post fire operations can be performed on the ceramic substrate layers.
• a temperature release tape such as P/N 3195M, available from Nitto Denko Co., Ltd. of Hong Kong, can be used to facilitate stacking of substrate layers during the lamination process.
• the amount of capacitance formed between the electrodes 465, 467, 470 and the grounded conductors is primarily a function of the relative permittivity of the substrate layers 110, 120, 130, 140, the surface area of the electrodes 465, 470, and the proximity of the surface of the electrodes to the grounded conductors. Accordingly, the surface area of the electrodes, the permittivity of the substrate layers 110, 120, 130, 140, and the distance between the substrates and the grounded conductors can be selected to achieve a desired capacitance value.
• the capacitance values depend from the surface area of the electrodes, the permittivity of the substrate, and the distance between the electrodes and the grounded conductors.
• an electrode 585 which is electrically coupled to a conductive layer 590 can be provided.
• Such a configuration can be used to provide a high capacitance value, for instance in excess of 10 nF, between the conductive layer 590 and the grounded conductors 595.
• the conductive layer 590 can be disposed between grounded conductive layers 597, 598. Such an arrangement can result in a larger capacitance value in comparison to an instance where only a single grounded conductive layer is provided.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Inorganic Chemistry (AREA)
• Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
• Ceramic Capacitors (AREA)
• Parts Printed On Printed Circuit Boards (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)

Applications Claiming Priority (2)

Publications (2)

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Family Applications (1)

Country Status (8)

Families Citing this family (5)

Family Cites Families (20)

• 2004
  • 2004-04-02 US US10/816,637 patent/US6908809B1/en not_active Expired - Lifetime
• 2005
  • 2005-03-28 CN CN2005800101533A patent/CN1938799B/zh not_active Expired - Fee Related
  • 2005-03-28 JP JP2007506426A patent/JP2007531326A/ja active Pending
  • 2005-03-28 WO PCT/US2005/010300 patent/WO2005099028A2/en not_active Ceased
  • 2005-03-28 EP EP05744369A patent/EP1738431A4/de not_active Withdrawn
  • 2005-03-28 KR KR1020067020534A patent/KR100859894B1/ko not_active Expired - Lifetime
  • 2005-03-28 CA CA2561955A patent/CA2561955C/en not_active Expired - Fee Related
  • 2005-03-30 US US11/093,543 patent/US7154139B2/en not_active Expired - Lifetime
  • 2005-03-31 TW TW094110388A patent/TWI258203B/zh not_active IP Right Cessation
• 2010
  • 2010-04-12 JP JP2010091052A patent/JP5156048B2/ja not_active Expired - Fee Related

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