EP1829099A1 - Verfahren zur behandlung der oberfläche eines wafers - Google Patents
Verfahren zur behandlung der oberfläche eines wafersInfo
- Publication number
- EP1829099A1 EP1829099A1 EP05823924A EP05823924A EP1829099A1 EP 1829099 A1 EP1829099 A1 EP 1829099A1 EP 05823924 A EP05823924 A EP 05823924A EP 05823924 A EP05823924 A EP 05823924A EP 1829099 A1 EP1829099 A1 EP 1829099A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- bonding
- wafer
- donor
- cleaning
- solution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Definitions
- the present invention relates to the bonding of two wafers comprising semiconductor materials, in order to produce structures that can be used in the fields of microelectronics, optics or optoelectronics.
- the invention relates more specifically to the activation of the bonding surface of at least one of the two wafers to be bonded, and this, while this latter has optionally been oxidized and / or has undergone implantation of atomic species. .
- Such an implantation of atomic species makes it possible to form an embrittlement zone, within a so-called "donor" wafer, at a determined depth.
- the quality of the bonding is essential to achieve a good layer transfer, the quality of this bonding being mainly measured by the bonding energy bonding the two wafers.
- the implantation step generally brings hydrocarbon-type contaminants to the platelet surface. In the presence of isolated particles or localized surface defects, this contamination can lead to the formation of superficial blisters, after detachment of the thin film and its transfer to the receptor plate, or even to the formation of non-transferred zones.
- substrates of the SOI type in which the buried oxide layer is very thin, that is to say less than 50 nm (50 nanometers) are more difficult to produce because much more sensitive to the appearance of defects of the "blistering" type. It is therefore also important to reinforce the bonding energy to extend the conditions of use and the application possibilities of the aforementioned "Smart Cut TM” method.
- the bonding energy must also be reinforced, in order to favor a detachment and a correct layer transfer. Indeed, the existence of contaminants at the bonding interface can lead to a detachment of the layer, at this interface, and not at the weakening zone, thereby creating defects (areas not transferred) on the receptor plate, which correspond to residues on the donor wafer. The lower the bonding energy, the greater the amount of non-transferred areas.
- the bonding wave has more difficulties to reach the edge of the wafer diametrically opposite to that where the bonding was initiated and there is a greater number defects in this region.
- several surface treatment processes are known beforehand in the state of the art, before bonding.
- cleaning before bonding a second cleaning step, carried out immediately before bonding and hereinafter referred to as "cleaning before bonding".
- the cleaning step a) surfaces to be bonded aims to: - make these surfaces hydrophilic
- RCA cleaning and activation process
- SCl a first bath of a solution known by the acronym "SCl” (according to the English terminology of "Standard Clean 1” which means “standard cleaning solution 1”), and which comprises a mixture of hydroxide ammonium (NH 4 OH), hydrogen peroxide (H2O2) and deionized water, - a second bath of a solution known by the acronym "SC2"
- Standard Clean 2 which means “standard cleaning solution 2”
- standard cleaning solution 2 which comprises a mixture of hydrochloric acid (HCl), hydrogen peroxide (H2O2) and deionized water.
- the first bath is intended primarily to remove the isolated particles present on the surface of the wafer and make the surfaces hydrophilic, while the second bath is rather intended to remove metal contamination.
- WO-2005/096369 a method of cleaning the oxidized surface of a wafer, for its bonding to another wafer.
- Such a process uses a mixture of ammonia (NH 4 OH) and hydrogen peroxide (H2O2) and allows to remove the isolated particles, while avoiding creating a surface roughness.
- step b) cleaning before bonding is very specific, since it conditions the quality of the substrates obtained after the layer transfer step (s).
- This step is intended to remove the particles that may have settled during the waiting time between the cleaning step a) and the bonding. It also aims to enhance the hydrophilicity of the pads, the latter having a tendency to significantly decrease the waiting time between the cleaning step a) and the bonding is long.
- This cleaning step b) is generally carried out by brushing the surfaces to be bonded with a deionized water solution, see for example on this subject the patent application FR 2 854 493.
- the present invention aims to overcome the aforementioned drawbacks and to introduce a chemical activation of the surfaces, during the cleaning step before bonding, preferably carried out at room temperature, in order to simplify the preliminary step a) cleaning, or even to remove it.
- the invention also aims, if the preliminary cleaning step a) is maintained, to increase the duration of the storage and activation time platelets between this cleaning step a) and the cleaning step before bonding according to the invention, while maintaining a high bonding energy, after the bonding of the two wafers.
- the activation step according to the invention must also be integrated in the best industrial process for manufacturing SOI type substrates, already existing.
- the invention relates to a method of treating one or the other or both surfaces, called “gluing” a first wafer, called “donor” and a second wafer, called “ receiver “, intended to be glued against each other, for the purpose of manufacturing a structure used in the field of optics, electronics or optoelectronics.
- this process comprises a cleaning and activation step, carried out immediately before the gluing of said donor and receiver platelets, by application to said one or more bonding surfaces of a so-called "surface treatment” solution.
- a so-called "surface treatment” solution comprising at least about 97% of a solution of ammonia (NH 4 OH) in water, preferably deionized, in a mass concentration of between about 0.05% and 2%.
- the treatment solution consists of a solution of ammonia (NH 4 OH) in water, preferably deionized, in a mass concentration of between about 0.05% and 2%;
- the treatment solution consists of approximately 97% of a solution (NH 4 OH) in water, preferably deionized, in a mass concentration of between approximately 0.05% and 2% and approximately 3% by weight.
- a solution NH 4 OH
- chelating agents and / or surfactants e.g., sodium EDTA, sodium EDTA, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisulfite, sodium metabisul
- the ammonia solution (NH 4 OH) has a mass concentration in water of between approximately 0.5% and 1.6%, more preferably around 0.8%;
- the cleaning and activation step is carried out by applying said surface treatment solution at a temperature less than or equal to
- the surface treatment solution is applied directly to the gluing machine, preferably for a period of between 10 seconds and 2 minutes;
- Said cleaning and activation step is performed by performing simultaneously the application of said surface treatment solution and the brushing of the bonding surface to be treated;
- At least one of the two bonding surfaces is covered with an oxide layer
- the donor wafer has undergone implantation of atomic species before bonding, so as to form a weakening zone, delimiting a thin layer to be transferred.
- the invention also relates to a method of manufacturing a structure intended to be used in the field of optics, electronics or optoelectronics.
- this method comprises the following steps:
- This method comprises a consolidation annealing step between the bonding step and the detaching step;
- the donor wafer is made of a semiconductor material, silicon or constrained silicon. This method makes it possible in particular to manufacture a structure of the semiconductor on insulator or silicon on insulator (SOI) type.
- FIGS. 1a to 1d represent the main steps of a method for sampling and transfer of layers, applied to the production of an SOI type substrate;
- FIG. 2 is a diagram representing a technique for measuring energy gluing between two platelets,
- FIG. 3 is a graph representing the bonding energy ⁇ between two wafers, as a function of the temperature of the annealing treatment, for platelet series having respectively undergone either a "control" cleaning and activation method, or the cleaning and activation process before bonding according to the invention,
- FIG. 4 is a graph illustrating the results of the measurement of the number of transfer defects in a reported layer, from series of platelets having respectively undergone either a "control" cleaning and activation method, or the method of cleaning and activation before bonding according to the invention
- FIG. 5 shows the evolution of the value of the bonding energy ⁇ between two platelets, for batches of platelets having undergone a first cleaning treatment, then a second cleaning and activation treatment immediately before bonding, but shifted in time compared with the first cleaning, this second treatment being either a "control" cleaning or a treatment according to the invention.
- a main objective of the present invention is to reduce the importance of defects and surface roughness, of at least one of two plates to be glued against each other, in order to increase the energy bonding between these pads.
- the invention applies more particularly to platelets covered with an oxide layer, this oxide being either "native", that is to say resulting from the oxidation in the open air of the wafer, or additional and resulting from a thermal treatment of this wafer or deposition of an oxide layer, for example.
- the invention finds particular application in the implementation of a method of manufacturing an SOI type substrate.
- a first step consists in oxidizing a wafer made of semiconductor material 13, so as to form a donor wafer 10 having on the surface an oxide layer 11.
- this oxidation results from a heat treatment or the deposition of an oxide layer, for example an SiO 2 layer when the wafer 13 is made of silicon.
- the donor wafer 10 is subjected, through one of its oxidized surfaces, to an implantation of atomic species (s), such as an implantation of hydrogen and / or helium, for example.
- atomic species such as an implantation of hydrogen and / or helium, for example.
- the energy and the doses of this implantation are chosen so as to form an embrittlement zone 15, at a determined depth below the surface of the donor wafer 10, more precisely inside the wafer 13. thin 16, delimited on the one hand by the weakening zone 15 and on the other hand by the oxide layer 11.
- the oxidized surface of the donor wafer 10, which has been implanted, is designated by the reference numeral 12.
- the surfaces 12 and 22, which are bonded by molecular adhesion, are then brought into contact with each other.
- an annealing step is optionally implemented to reinforce the bonding interface 17 between the donor and recipient platelets 20.
- an energy of thermal, mechanical and / or chemical origin sufficient to carry out the detachment along the embrittlement zone 15 and thereby detach the thin layer 16, from the rest 18 of the donor plaque.
- the semiconductor-on-insulator structure shown in FIG. 1D is thus obtained, the thin layer 16 taken from the donor wafer 10 forming the semiconductor portion and the underlying oxide layer 11 forming the electrically insulating portion.
- This structure is referenced 30.
- a finishing step, using, for example, a chemical-mechanical polishing, is then optionally implemented to make up for any defects or roughness occurring during the detachment of the thin layer 16.
- the final structure 30 thus obtained is intended for applications in the field of microelectronics, optics or optoelectronics.
- the receptor plate 20 could possibly be covered with a layer of oxide, in particular native oxide.
- the object of the invention is to provide a method of cleaning and activation, surfaces to be bonded, that is to say in the above example, surfaces 12 and / or 22. This method not only allows to remove contaminants or isolated particles, but also to activate surfaces to stick.
- the applicant has observed that the treatment of the bonding surfaces of two wafers to be bonded, or at least one of these surfaces, with the aid of a specific solution made it possible to increase the bonding energy between these two wafers.
- this solution is called "surface treatment”.
- This surface treatment solution comprises at least about 97% of a solution of ammonia (NH 4 OH) in water, preferably deionized, in a mass concentration of between about 0.05% and 2%.
- the surface treatment solution consists of a solution of ammonia (NH 4 OH) in water, preferably deionized, in a mass concentration of between about 0, 05% and 2%,
- This solution of ammonia is a pure solution, that is to say a solution whose concentration of pollutant type metallic contaminants (copper, iron, chromium, titanium, nickel, aluminum) and / or alkaline contaminants, (lithium, sodium, calcium, potassium, etc.) do not exceed a concentration of 10 ppt (part per trillion) for each element.
- a surface treatment solution consisting of approximately 97% of the abovementioned ammonia solution and approximately 3% of chelating agents and / or surfactants is used.
- chelating agents indeed make it possible to fix the contaminants, such as metals or ions in solution, which are often present in the commercially available ammonia and which might remain trapped at the bonding interface, thereby modifying the electrical characteristics of the final substrate obtained.
- the surfactant makes it possible to increase the efficiency of removal of particles that can lead to the formation of superficial blisters.
- the mass concentration of the ammonia solution is between 0.5% and 1.6%, or better still close to 0.8%.
- the ammonia solution mentioned above is used at room temperature. It can, however, be applied at higher temperatures but preferably not exceeding 70 ° C. Indeed, at higher temperatures, the roughness of the surfaces increases sharply, which leads to an increase in the number of defects of the "blister" type.
- the aforementioned cleaning and activation treatment is carried out immediately before gluing, preferably directly on the gluing machine, in order to reactivate the hydrophilicity of the wafers put in contact, even if they have been waiting for several hours after the cleaning step, as will be detailed later.
- the activating solution can be distributed, either directly on the wafers to be treated without brushing, or directly on the brushes used for activation or on the wafers, before a subsequent brushing.
- the ammonia solution is preferably delivered for a period of 10 seconds to 2 minutes, preferably 30 seconds to 1 minute, at a flow rate of the order of 1.5 1 / min and directly at the gluing equipment, for example using a distributor arm.
- the ammoniacal solution may be dispensed from specific cleaning equipment, for example by spraying (equipment of the "single wafer” type) or of the bath type (equipment of the "wet bench” type).
- the Applicant has carried out a comparative study of the bonding energy at the interface between two wafers, with series of wafers having respectively undergone either a so-called "control" cleaning and activation process, or the method according to US Pat. the invention.
- the Applicant has inserted a blade 40 on one or more edges of the set of plates 10 and 20 in contact with each other, at the interface of FIG. collage 17.
- the length L between the outer edge of the plates 10, 20 and the stopping point of the detachment, which corresponds to the sum of the length of the area locally peeled off by the blade 40 and the length of the propagation of the separation zone gives an indication of the bonding energy that exists between the two wafers 10 and 20.
- the end of the separation corresponds to a balance between the bonding energy and the elastic deformation characterizing the detachment.
- FIG. 3 represents the bonding energy ⁇ , as a function of the temperature of a possible annealing treatment (called “consolidation treatment”), carried out for 2 hours. Some of the structures did not undergo this subsequent consolidation treatment (results obtained when the temperature is close to 20 ° C), and others have undergone this treatment for 2 hours, at various temperatures.
- control treatment The dotted line curve represents the results obtained with the batches, in which the platelet bonding surfaces have undergone a water rinsing treatment and simultaneous brushing activation, this treatment being carried out immediately before bonding. This treatment is hereinafter referred to as "control" treatment.
- the solid line represents the results obtained with the batches, in which the platelet bonding surfaces have undergone the cleaning and activation treatment in accordance with the invention.
- the ordinate axis represents the number of transfer defects N measured, per plate.
- the abscissa axis represents the results obtained, on the one hand with the control batches Te, for which the surface treatment step was carried out according to the "control" method mentioned above, and on the other hand, with the batches I , in which the cleaning and activation step has been carried out in accordance with the invention, as described with reference to FIG.
- the average number of transfer defects N in the first case is 4.09, while it is close to 0.83 in the second case.
- Both wafers were silicon and measured eight inches in diameter (200 mm).
- the first cleaning treatment was of the aforementioned RCA type.
- the cleaning and activation treatment according to the invention was carried out by brushing, under a dilute ammonia solution, at a mass concentration of less than 0.5%, in deionized water.
- the solid line represents the results obtained with platelets having undergone the "control" surface treatment described in conjunction with FIGS. 3 and 4.
- the dotted line represents the results obtained with platelets having undergone the cleaning and activation treatment according to the invention.
- the applicant has highlighted the interest of implementing the cleaning and activation method according to the invention, in a method of sampling and transfer of layer, and more specifically in the manufacture of an SOI type substrate.
- the method according to the invention makes it possible to increase the bonding energy, which makes it possible to be less demanding concerning the criteria for carrying out a first cleaning carried out a certain time before bonding, or even to completely eliminate it. this.
- the activation method according to the invention makes it possible to reduce the number of edge plate transfer defects to less than one per plate on average, thereby considerably increasing the quality of the thin layer. in which the future electronic components will be made.
- the present invention is not limited to an activation method for bonding two silicon wafers, at least one of which is coated with a silicon oxide layer, but can be extended to any type of material, such as constrained silicon or other semiconductor material that can be used in Smart Cut TM technology.
Landscapes
- Cleaning Or Drying Semiconductors (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0413922A FR2880185B1 (fr) | 2004-12-24 | 2004-12-24 | Procede de traitement d'une surface de plaquette |
| FR0413930A FR2880186B1 (fr) | 2004-12-24 | 2004-12-24 | Procede de traitement d'une surface de plaquette |
| PCT/EP2005/057003 WO2006069945A1 (fr) | 2004-12-24 | 2005-12-21 | Procédé de traitement d'une surface de plaquette |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1829099A1 true EP1829099A1 (de) | 2007-09-05 |
Family
ID=36202757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP05823924A Withdrawn EP1829099A1 (de) | 2004-12-24 | 2005-12-21 | Verfahren zur behandlung der oberfläche eines wafers |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7919391B2 (de) |
| EP (1) | EP1829099A1 (de) |
| JP (1) | JP2008526006A (de) |
| KR (1) | KR100884672B1 (de) |
| TW (1) | TWI333258B (de) |
| WO (1) | WO2006069945A1 (de) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2868599B1 (fr) * | 2004-03-30 | 2006-07-07 | Soitec Silicon On Insulator | Traitement chimique optimise de type sc1 pour le nettoyage de plaquettes en materiau semiconducteur |
| FR2890489B1 (fr) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant |
| FR2920912B1 (fr) * | 2007-09-12 | 2010-08-27 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure par transfert de couche |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| CN107958835A (zh) * | 2016-10-14 | 2018-04-24 | 上海新昇半导体科技有限公司 | 一种半导体晶圆的抛光方法 |
| FR3102771B1 (fr) * | 2019-10-31 | 2021-10-08 | Commissariat Energie Atomique | Procédé de collage de deux surfaces hydrophiles |
| FR3106235B1 (fr) * | 2020-01-09 | 2021-12-10 | Soitec Silicon On Insulator | Procede d’assemblage de deux substrats semi-conducteurs |
| FR3136107B1 (fr) * | 2022-05-25 | 2024-05-31 | Commissariat Energie Atomique | Procédé de collage direct assisté par une base forte |
| FR3136106B1 (fr) * | 2022-05-25 | 2024-05-31 | Commissariat Energie Atomique | Procédé de collage direct assisté par une molécule basique |
| FR3136108B1 (fr) | 2022-05-25 | 2024-04-19 | Commissariat Energie Atomique | Procédé de collage direct assisté par des élements cationiques |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS5392666A (en) * | 1977-01-25 | 1978-08-14 | Seiko Epson Corp | Manufacture of semiconductor device |
| JP2738063B2 (ja) * | 1989-10-05 | 1998-04-08 | 富士通株式会社 | 接合シリコン基板の製造方法 |
| JP3187109B2 (ja) | 1992-01-31 | 2001-07-11 | キヤノン株式会社 | 半導体部材およびその製造方法 |
| JPH07183288A (ja) | 1993-12-24 | 1995-07-21 | Toshiba Corp | 半導体ウェーハ処理剤 |
| US5916819A (en) * | 1996-07-17 | 1999-06-29 | Micron Technology, Inc. | Planarization fluid composition chelating agents and planarization method using same |
| US6896826B2 (en) * | 1997-01-09 | 2005-05-24 | Advanced Technology Materials, Inc. | Aqueous cleaning composition containing copper-specific corrosion inhibitor for cleaning inorganic residues on semiconductor substrate |
| US6159824A (en) * | 1997-05-12 | 2000-12-12 | Silicon Genesis Corporation | Silicon-on-silicon wafer bonding process using a thin film blister-separation method |
| JPH1197379A (ja) * | 1997-07-25 | 1999-04-09 | Denso Corp | 半導体基板及び半導体基板の製造方法 |
| US6211558B1 (en) * | 1997-07-18 | 2001-04-03 | Kavlico Corporation | Surface micro-machined sensor with pedestal |
| US6376337B1 (en) * | 1997-11-10 | 2002-04-23 | Nanodynamics, Inc. | Epitaxial SiOx barrier/insulation layer |
| JP3697106B2 (ja) | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
| JP3385972B2 (ja) * | 1998-07-10 | 2003-03-10 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法および貼り合わせウェーハ |
| JP3328250B2 (ja) * | 1998-12-09 | 2002-09-24 | 岸本産業株式会社 | レジスト残渣除去剤 |
| US6171965B1 (en) * | 1999-04-21 | 2001-01-09 | Silicon Genesis Corporation | Treatment method of cleaved film for the manufacture of substrates |
| US6799583B2 (en) * | 1999-05-13 | 2004-10-05 | Suraj Puri | Methods for cleaning microelectronic substrates using ultradilute cleaning liquids |
| US6653209B1 (en) * | 1999-09-30 | 2003-11-25 | Canon Kabushiki Kaisha | Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device |
| JP3307375B2 (ja) * | 1999-10-04 | 2002-07-24 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP3943782B2 (ja) * | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
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| US7235461B2 (en) * | 2003-04-29 | 2007-06-26 | S.O.I.Tec Silicon On Insulator Technologies | Method for bonding semiconductor structures together |
| FR2854493B1 (fr) * | 2003-04-29 | 2005-08-19 | Soitec Silicon On Insulator | Traitement par brossage d'une plaquette semiconductrice avant collage |
| US6875087B2 (en) * | 2003-05-13 | 2005-04-05 | Novellus Systems, Inc. | Method for chemical mechanical planarization (CMP) and chemical mechanical cleaning (CMC) of a work piece |
| US7232759B2 (en) * | 2004-10-04 | 2007-06-19 | Applied Materials, Inc. | Ammonium hydroxide treatments for semiconductor substrates |
-
2005
- 2005-06-02 US US11/145,455 patent/US7919391B2/en not_active Expired - Fee Related
- 2005-12-21 JP JP2007547504A patent/JP2008526006A/ja active Pending
- 2005-12-21 KR KR1020077014457A patent/KR100884672B1/ko not_active Expired - Fee Related
- 2005-12-21 EP EP05823924A patent/EP1829099A1/de not_active Withdrawn
- 2005-12-21 WO PCT/EP2005/057003 patent/WO2006069945A1/fr not_active Ceased
- 2005-12-23 TW TW094145970A patent/TWI333258B/zh not_active IP Right Cessation
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2006069945A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20060141746A1 (en) | 2006-06-29 |
| KR100884672B1 (ko) | 2009-02-18 |
| JP2008526006A (ja) | 2008-07-17 |
| US7919391B2 (en) | 2011-04-05 |
| WO2006069945A1 (fr) | 2006-07-06 |
| TW200636906A (en) | 2006-10-16 |
| TWI333258B (en) | 2010-11-11 |
| KR20070088737A (ko) | 2007-08-29 |
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