EP1859480A1 - Production d'un contact de plaquette substrat dans des circuits soi integres a tranchee isolee, ayant des composants haute tension - Google Patents

Production d'un contact de plaquette substrat dans des circuits soi integres a tranchee isolee, ayant des composants haute tension

Info

Publication number
EP1859480A1
EP1859480A1 EP06722586A EP06722586A EP1859480A1 EP 1859480 A1 EP1859480 A1 EP 1859480A1 EP 06722586 A EP06722586 A EP 06722586A EP 06722586 A EP06722586 A EP 06722586A EP 1859480 A1 EP1859480 A1 EP 1859480A1
Authority
EP
European Patent Office
Prior art keywords
trench
layer
polysilicon
trenches
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06722586A
Other languages
German (de)
English (en)
Inventor
Ralf Lerner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Publication of EP1859480A1 publication Critical patent/EP1859480A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment

Definitions

  • the invention relates to a method of simultaneous production of carrier wafer contacts and isolation trenches of integrated circuits with high voltage components for thick active silicon layers with thicknesses equal to or greater than 50 ⁇ m on the basis of SOI technology and the corresponding trench structuring.
  • the carrier wafer ("handle wafer") is electrically isolated.
  • an electrical contact is desirable. This can sometimes be done from the back of the wheel. But it may also be necessary or advantageous to realize the contact from the front. This contact with the carrier disk then allows the application of a defined electrical potential to the carrier disk.
  • the carrier disk floats, i. it can be at fluctuating electrical potential and thereby adversely affect the electrical function of the integrated circuits on the top of the active disk ("floating body effect").
  • Trench isolation is often used here, especially in technologies that use SOI disks with thick, eg at least 50 ⁇ m, active silicon layers.
  • US-A-6,794,716 also describes a method in which a trench which extends below the buried oxide is filled with "metal” and tungsten and thus a contact region in the carrier wafer with a portion of the active layer ("Body" of a transistor) conductively connects.
  • US Pat. No. 6,521,947 uses a method which is similar in principle to the previously mentioned method. Instead of metal polysilicon is used there as a contacting material.
  • This method has the following disadvantages: at least two structuring steps are required. Due to the metallization carried out no high-temperature processes can be carried out following this process. Due to the doped spacer, the carrier disk is permanently connected to the active disk. An insulated from the active silicon wafer contacting the carrier disk is thus not possible. In the structure described, all regions of the active layer are connected to the carrier wafer and thus short-circuited.
  • this structure has the disadvantage that for the production of the same a method has to be used in which two different structuring and two different etching steps have to be used for the isolation trench and the contact. This means on the one hand effort, on the other hand, this means that this structure can not be used in this form for deep isolation trenches, typical depth 50 ⁇ m.
  • the object of the invention is to specify a method with which such structures can be produced which enable both trench isolation and carrier disk contacting of SOI disks with thick (greater than or equal to 50 ⁇ m) active layers and which can be produced much more easily with a few process steps ,
  • a trench structure fabrication approach is disclosed that can be used both as a trench isolation and as a support wafer contact for substantially 50 ⁇ m thick or thicker active silicon layers of SOI wafers with integrated high voltage devices and incorporating the same process steps, i. can be produced with little effort.
  • the invention has the advantages that with the same process steps both an isolation trench for isolation against high voltages and a conductive contact trench to the carrier disk is produced.
  • the starting point for contact arising from a trench with a conductive filling layer is a wider trench.
  • Starting point for the insulating trench which is filled with a dielectric filling layer, a narrower trench, which are adjacent.
  • These trenches are first introduced into the active layer with an etching step, wherein a masking layer specifies where the trenches are to be formed in their depth to the buried insulating layer of the SOI wafer.
  • the width of the trenches is different.
  • the wider trench is up to three times wider than the narrower trench (claim 17), but at least the wide trench will be substantially 50% wider than the narrower trench.
  • An insulating layer is formed, which relates to both trenches, being arranged at least on the side wall of the trenches, but may also be arranged at the bottom, where this insulating layer superimposes the buried oxide layer.
  • the narrower trench is filled, and the wider trench just not completely filled, but only covered on its side walls with the insulating layer of the first backfill material.
  • the full filling of the narrower trench will cause the soil to be covered and in the wider trench this soil will also be covered.
  • High-barrier components are not explicitly drawn, can be introduced before or after the manufacturing steps described herein in the active substrate, this processed substrate with the two different functional trenches has the property of such - high-voltage blocking - semiconductors for appropriate semiconductor technologies.
  • the insulating first layer which completely fills the narrower trench is a polysilicon.
  • the masking layer is also provided with a thickness that is larger (stronger) than the buried oxide layer.
  • the layers lying on the surface are subject to just such a reduction in their strength, for example the first backfill layer filling the narrow trench, which later in the wider trench, it is not completely filled out.
  • the surface of this layer outside the trench is also reduced in its layer thickness.
  • planarization of the surface may still occur, carried out so that all layers perpendicular to the trenches terminate at this planar surface, with the wider trench having more vertically oriented, parallel layers than the narrower trench.
  • FIG. 1 shows schematically in cross-section an insulating trench in an SOI layer arrangement, which corresponds to the prior art.
  • the starting material in FIG. 1 is an SOI disk in which the carrier disk 1 is electrically insulated from the active silicon layer 3 by a buried oxide 2.
  • the isolation trench 6 consists of an insulating layer 4, e.g. Silica on the sidewalls of the trench and a backfill layer 5, e.g. Polysilicon can be.
  • an SOI disk consisting of the carrier disk 1, the buried insulator 2 and the active silicon layer or disk 3 is formed and a masking layer 7 is formed and patterned on the active silicon layer 3, which in one embodiment is silicon dioxide is constructed, while in other embodiments, other suitable materials, such as silicon nitride, can be used, see Fig. 2.
  • the masking layer 7 is provided as an oxide layer and therefore the layer is also referred to as a masking oxide layer 7, which then has a thickness which is greater than the thickness of the layer 2 as a buried oxide.
  • the masking layer 7 can also be produced with a smaller thickness. With the aid of the masking layer 7, trenches 8 and 9 having different widths are etched down to the buried oxide layer 2, see FIG. 3.
  • a trench isolation layer 10 (depositing) is deposited or formed (thermally).
  • this trench isolation layer 10 is a CVD layer.
  • a remaining trench 9 1 or 8 1 is less wide than the one Exit trenches 9 and 8, respectively.
  • a trench isolation layer 10 ' (not separately illustrated, but well conceivable by those skilled in the art) is formed substantially selectively on the trench sidewalls by thermal oxidation.
  • the narrow trench 8 ' is filled with a filling layer 18, the wide trench 9' is lined only on the opposite trench side walls, i. not completely filled, as shown in Figure 5. There remains an even narrower open trench 9 ", laterally and down bounded by the deposited layer portions 11a, 11b and 11c of the layer 11 in the first embodiment.
  • FIG. 6 shows the structure after a polysilicon etching step.
  • the polysilicon 11 has been removed at the surface and trench bottom 9a in the wide trench 9 ", so that the trench isolation layer 10 is exposed with its bottom portion 10a when formed by CVD deposition.
  • the buried layer 2 is exposed by this etching step.
  • the narrow trench 8 remains filled with polysilicon.
  • a polysilicon spacer 12 remains on each side wall.
  • FIG. 7 shows the structure after an oxide etching, preferably by means of a plasma chemical etching, in which the buried oxide 2 at the bottom 9a of the recrossed trench 9 ** and the layer 10a (as part of the layer 10) were etched through at the bottom.
  • the layer section 10a is substantially not formed at the trench bottom and thus essentially only the buried layer 2 is etched through.
  • a part of the oxide in the embodiment shown is removed from the surface. Since the masking layer 7, if made of oxide, had a greater thickness than the buried oxide layer 2, a residual oxide layer 13 remains on the surface.
  • the narrower isolation trench 8 with insulating filler 18 on the left side in FIG. 7 remains completely filled.
  • a second filling layer 14 with a corresponding electrical conductivity also fills the wider isolation trench 9 here in width as 9 ** with conductive filling material 19, see FIG. 8.
  • the surface 20 becomes CMP (chemical mechanical polishing) preferably planarized, see FIG. 9.
  • Components such as high-blocking semiconductors, for example MOSFET with reverse voltages above 300 V, can be introduced onto or into the active layer; Methods of semiconductor technology are known.
  • the carrier disk 1 can be electrically contacted from the surface. Next to it is an insulating trench 8 available. The substrate no longer float potential.
  • insulating layer eg SiO 2
  • filling layer e.g. polysilicon

Landscapes

  • Element Separation (AREA)

Abstract

L'invention concerne un procédé de production de structures qui permettent tant une isolation de tranchées qu'une mise en contact de plaquettes SOI aux couches actives épaisses et qui sont faciles à produire en peu d'étapes. A cet effet, le contact électrique de plaquette substrat et la tranchée d'isolation sont réalisés avec des composants à haut pouvoir de blocage dans une plaquette SOI destinée à des circuits intégrés. Deux tranchées, une tranchée étroite destinée à la tranchée d'isolation (8) et une tranchée large destinée au contact de plaquette substrat (9), sont creusées par gravure jusqu'à la couche d'oxyde isolant (2) enfouie à l'aide d'une couche de masquage qui est plus épaisse que la couche d'oxyde (2) enfouie. Dans la large tranchée (9), un espaceur de polysilicium (12) reste respectivement sur les parois latérales en tant que reste d'une couche de polysilicium (11) préalablement déposée. Le réglage de la gravure de polysilicium permet d'obtenir un espaceur (12) de la hauteur souhaitée. Au moins l'oxyde (2;10) enfoui est enlevé par gravure du fond de la large tranchée (9) de telle façon qu'une couche d'oxyde résiduelle (13) demeure à la surface. Le dépôt d'une deuxième couche de remplissage (14) à conductivité électrique remplit également la large tranchée d'isolation (19).
EP06722586A 2005-03-10 2006-03-10 Production d'un contact de plaquette substrat dans des circuits soi integres a tranchee isolee, ayant des composants haute tension Withdrawn EP1859480A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005010944A DE102005010944B4 (de) 2005-03-10 2005-03-10 Verfahren zur Herstellung eines Trägerscheibenkontaktes in integrierten Schaltungen mit Hochspannungsbauelementen auf der Basis der SOI-Technologie und integrierte Schaltungen mit entsprechenden Grabenstrukturen
PCT/DE2006/000429 WO2006094495A1 (fr) 2005-03-10 2006-03-10 Production d'un contact de plaquette substrat dans des circuits soi integres a tranchee isolee, ayant des composants haute tension

Publications (1)

Publication Number Publication Date
EP1859480A1 true EP1859480A1 (fr) 2007-11-28

Family

ID=36731250

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06722586A Withdrawn EP1859480A1 (fr) 2005-03-10 2006-03-10 Production d'un contact de plaquette substrat dans des circuits soi integres a tranchee isolee, ayant des composants haute tension

Country Status (6)

Country Link
US (1) US8053897B2 (fr)
EP (1) EP1859480A1 (fr)
JP (1) JP2008533705A (fr)
KR (1) KR20070118626A (fr)
DE (1) DE102005010944B4 (fr)
WO (1) WO2006094495A1 (fr)

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IT202200024708A1 (it) * 2022-11-30 2024-05-30 St Microelectronics Srl Dispositivo semiconduttore ad alta tensione avente un isolamento a trincea profonda e processo di fabbricazione

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Also Published As

Publication number Publication date
WO2006094495A1 (fr) 2006-09-14
DE102005010944B4 (de) 2009-09-10
DE102005010944A1 (de) 2006-09-14
US20080283960A1 (en) 2008-11-20
KR20070118626A (ko) 2007-12-17
US8053897B2 (en) 2011-11-08
JP2008533705A (ja) 2008-08-21

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