EP1897264A2 - Rahmensynchronisationsverfahren und -einrichtung - Google Patents
Rahmensynchronisationsverfahren und -einrichtungInfo
- Publication number
- EP1897264A2 EP1897264A2 EP06709524A EP06709524A EP1897264A2 EP 1897264 A2 EP1897264 A2 EP 1897264A2 EP 06709524 A EP06709524 A EP 06709524A EP 06709524 A EP06709524 A EP 06709524A EP 1897264 A2 EP1897264 A2 EP 1897264A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- frame
- syndrome
- received frame
- window
- equal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
Definitions
- the present invention relates to the field of telecommunications. Within this field, the invention relates more particularly to so-called digital communications. Digital communications include in particular wireless communications whose channel of transmission is the air channel as well as wired communications.
- Digital communications increasingly use more or less sophisticated channel coding.
- the principle of channel coding consists in adding to the information bits a controlled redundancy which will enable the receiver to detect the presence of transmission errors and possibly to correct them.
- the codes in blocks are more particularly distinguished: these codes correspond to a block of n b bits of information a code word of size n c bits with n c > n b . These additional bits make it possible to correct certain transmission errors; the more bits of redundancy and the better the correctness of the code.
- the receiver To decode and correct errors, the receiver must be able to find the beginning of the codewords in the bit sequence in order to be able to decode them correctly. This operation is commonly called frame synchronization.
- the invention relates to frame synchronization techniques.
- Frame synchronization is generally achieved by periodically adding in the message to be transmitted an uncoded synchronization sequence known to the receiver. This sequence is then detected at the receiver thus allowing the synchronization of the frame to be decoded.
- Such a sequence is described in the respective reference articles: "Optimum Frame Synchronization” by James L.Massey, IEEE Transactions on Communications, Vol.Com-20, No.2, April 1972 and “Frame Synchronization Techniques” by Robert A. Scholtz, 0090-6778 / 80 / 0800-1204 $ 00.75, 1980 IEEE.
- the technical problem to be solved by the object of the present invention is to propose a frame synchronization method constituting data of code words which does not have the disadvantage of known methods and which, therefore, offers greater efficiency spectral.
- said frame synchronization method consists in determining a start position D of a received frame T 1 , by means of a sliding window H on the received frame T. 1 , of size Kn c , divided into K blocks B 1 of size n c equal to that of a code word.
- the starting position D is equal to one of several possible positions of the sliding window H along the received frame T 1.
- the method is such that, for different possible positions of the window H, it calculates a syndrome Sj ' by block B 1 , the starting position D of the received frame T 1 .
- the subject of the invention is a device for synchronizing data frame constituting codewords, in order to determine a frame start position.
- the device comprises: windowing means sliding on a received frame T 1 of size Kn 1 , divided into K blocks Bj of size n L equal to that of a code word, the position D of received frame start T 1 being equal to one of several possible positions of the windowing means sliding along the received frame T 1 .
- a means for calculating a syndrome S ⁇ for different possible positions of the windowing means and for different blocks B 1 of the windowing means a means for determining a position for which the number of null elements of the SJ syndromes 1 1 calculated for this position is greater Ic, c ⁇ in case the calculation means determines a first number of zero elements syndromes ⁇ SJ, the frame start position D being equal to that position.
- a method and a device according to the invention which respectively relates to a synchronization method and a synchronization device, make it possible to determine the frame dcbtt1 position by taking it equal to the position of the sliding window which corresponds to the largest number of null elements.
- the method and the frame synchronization device according to the invention solve the problem. Indeed, the synchronization is of the self-taught type; it does not require any learning sequence. Synchronization relies solely on the properties of linear block coding.
- a synchronization according to the invention is particularly advantageous because the deletion of the synchronization sequence makes it possible either to increase the useful bit rate or to keep the same bit rate as before but to use codes having more bits of redundancy. that is to say to use lower efficiency codings and therefore having a greater correction power. And, as the number of redundancy bits increases, the synchronization performance of a method according to the invention increases.
- a frame synchronization according to the invention does not use any known sequence inserted in the coded frame; it does not therefore require a synchronization sequence. It works with any type of block code (BCH, RS, product code, LDPC, ). It does not require modifying the correcting code. It operates before decoding, that is, it does not take advantage of the coding gain. It is not very complex and is effective even in the presence of a high rate of binary error.
- the steps of the method are determined by the instructions of an uncorrected frame synchronization program in an electronic circuit such as a chip itself which can be arranged in an electronic device such as a receiver.
- the frame synchronization method according to the invention can equally well be implemented when this program is loaded into a computing device such as a processor or equivalent whose operation is then controlled by the execution of the program.
- the invention also applies to a computer program, including a computer program on or in an information carrier, adapted to implement the invention.
- This program may use any programming language, and be in the form of source code, object code, or intermediate code between source code and IeI object code only in a partially compiled form, or in any other form desirable to implement a method according to the invention.
- the information carrier may be any entity or device capable of storing the program. For example, little support! include storage means, such as a ROM, for example a CD ROM or a circuit ROM microclectronique, or a magnetic recording means, for example a diskette (floppy dise) or a hard disk.
- the information medium can be a transmissible medium such as an electrical or optical signal, which can be conveyed via an electrical or optical cable, by radio or by other means.
- the program according to the invention can be downloaded in particular on an Internet type network.
- the information carrier may be an integrated circuit in which the program is incorporated, the circuit being adapted to execute or to be used in the execution of the method in question.
- Figure 1 is a block diagram of the block coding for a Hamming code (7.4).
- Figure 2 is a diagram of the transmission delay of to bits of a transmitted frame.
- Figure 3 is a diagram of the principle of a synchronization method according to the invention.
- FIG. 4 is a diagram of an emitted frame and a received frame.
- FIG. 5 represents a sliding window of a method according to the invention, on a frame received for different positions d of the window.
- FIG. 6 schematically represents a first particular embodiment of a synchronization device according to the invention.
- Figure 1 shows a schematic block coding scheme for a Hamming code (7.4).
- the principle of block coding consists in adding to the information bits B ⁇ b 2 ,..., B 4 a redundancy c ⁇ , c h , c ⁇ controlled which will enable the receiver to detect the presence of transmission errors. and possibly correct them.
- the block codes correspond to a block of n b bits of information a code mole of size n c bits with n t > n h .
- the n c - n b redundancy elements are calculated as the sum of two of some bits of the information bit block.
- the Hamming code (7.4) in particular, has three redundancy bits such that each bit is calculated from three information bits. For example, the fifth bit of a coded codeword has ⁇ cc a code of
- Hamming (7.4) is equal to the sum modulo two of the second, third and fourth information bits:
- the code is said systematic if h n first bits of code word correspond to the n b bits of information. This is the case in our example.
- the receiver receives the transmitted code word, possibly tainted with errors due to the transmission channel.
- the receiver must be able to render the n b bits of information. This is the subject of a decoding operation.
- the optimal decoding on binary data is to find the remote code word of
- Hamming i.e. the number of distinct bits in a bit-to-bit comparison
- the principle of decoding codes in blocks is as follows.
- the receiver has n c - n h bits of redundancy to correct 2 "- 1 possible errors, so the receiver can only correct a fraction of the errors in an arbitrary way.
- low weight is preferred, that is the correction of the error vectors e having few non-zero elements
- P parity matrix
- the decoding method consists of calculating the syndrome $ (j) of the observation r:
- the decoding method derives from the table (2) an estimate of the error e. Then, sum the error estimate to the observation to perform the correction. If the syndrome is zero this means that r is a codeword.
- FIG. 2 introduces a transmission delay of to bits due to the transmission time between the transmitted frame T 1 and the received frame T 1 .
- this delay is not known prior to the receiver.
- the receiver To calculate the syndrome S (r k ) associated with the received code word r, the receiver must be able to estimate the transmission delay to; a synchronization method allows the receiver to estimate this delay to.
- a synchronization according to the invention, illustrated by FIG. 3, is performed by means of a sliding window H on the received frame T 1 .
- the window is divided into K blocks B, whose size is equal to that of a mol m tk of code, ie n t .
- the size of this synchronization window is therefore equal to Kn 1 so that once the synchronization is obtained, the window contains exactly K codewords.
- K is equal to three
- the method calculates a syndrome Sf for each position of the window on the frame, d being able to vary from zero to n L -1, and, for a given position, for each block B 1 .
- SJ ⁇ is therefore a vector of size n c -n b .
- the method can perform the calculation of syndromes for some positions of the window on the frame, and for these positions, for some blocks B 1 .
- the method calculates the number of null elements in the syndromes for a given position of the window H.
- the method takes as an estimate of t 0 , the position d for which the number of null elements for the syndromes associated with the same position of the window is the largest.
- the method according to the invention gives the same success rate as a method which consists in retaining the position of the window H for which the number of syndromes S j draws is the biggest.
- the syndromes associated with the K blocks are all zero.
- the process leads to K ⁇ n c -n b ) zero elements.
- the method according to the invention may be more advantageous and have a better success rate than a method which consists in retaining the position of the window H for which the number of syndromes S ⁇ nulls is the largest.
- FIGS. 4 and 5 correspond to a particular example of an encoding of the information bits by means of the Hamming code (7.4).
- FIG. 4 represents the transmitted frame T 1 and the received frame T 1 , According to the example, the received frame T 1 is delayed by one bit and contains two errors. The delay bit and the erroneous bits are shown in bold.
- the synchronization window is positioned by the receiver on the received frame. According to the example chosen, the size of the window is fourteen bits. The window can therefore cover two codewords.
- the window H is divided into two blocks Bi and B 2 of seven bits. From the bits of Bi, the method calculates the associated syndrome SJ 1 . The method repeats this operation for block B 2 to determine Sf syndrome.
- the number of null elements is equal to four and the number of syndromes S [, ⁇ S, zero is equal to zero.
- the method chooses a position among these different positions.
- This selected position determines the start position of the frame.
- the choice can be made arbitrarily, for example it can relate to the position corresponding to the smallest value of d.
- the choice may result from the implementation of a function including tests such as. for example, if the number of positions is odd then the selected position is the central position among the different positions.
- Another embodiment may be to increase the size of the synchronization window.
- FIG. 6 schematically represents a first particular embodiment of a synchronization device according to the invention.
- the device 1 comprises a windowing means 2 sliding on a received frame T t , a means 3 for calculating a syndrome S [ 1 ', a means 4 for determining a synchronization position D.
- the sliding windowing means 2 is of size Kn c . 11 is cut into K blocks B, of size H equal to that of a code word.
- the starting position D is equal to one of several possible positions of the windowing means 2 sliding along the received frame T 1.
- this windowing means 2 can include a battery of registers forming a delay line into which the bits of the received frame enter on a serial input.
- the window is sized by the choice of parallel outputs of the battery.
- the blocks B 1 are determined by the way in which these outputs are taken into account by the calculation means.
- the calculating means 3 calculates a syndrome S d for each of the K blocks B, the means 2 of windowing and for the different positions of this means 2 of windowing. Each syndrome being composed of elements, the calculation means 3 determines for a given syndrome the number N d of null elements of the syndrome. Typically, this calculation means 3 is a computer such as a microprocessor.
- the means 4 for determining a position determines the position for which the number N d of zero elements of a syndrome is the largest. The start position D is equal to this position. This means 4 can be part of the calculation means 3.
- a method and a synchronization device according to the invention operate with all types of codes in linear blocks.
- Flexible data means receiving data that has not yet been compared to a threshold to be declared equal to a zero or a bit.
- the flexible data therefore has a voltage level that can take values that are not just the voltage levels of a zero or a bit obtained after thresholding.
- the invention applies to any type of wired or wireless transmission system including the transmitting data are discrete, but may s is additionally applied to any storage system information.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0501748A FR2882480B1 (fr) | 2005-02-18 | 2005-02-18 | Procede et dispositif de synchronisation trame |
| PCT/FR2006/050145 WO2006087497A2 (fr) | 2005-02-18 | 2006-02-20 | Procede et dispositif de synchronisation trame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1897264A2 true EP1897264A2 (de) | 2008-03-12 |
Family
ID=34954531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP06709524A Ceased EP1897264A2 (de) | 2005-02-18 | 2006-02-20 | Rahmensynchronisationsverfahren und -einrichtung |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7995692B2 (de) |
| EP (1) | EP1897264A2 (de) |
| JP (1) | JP5214977B2 (de) |
| FR (1) | FR2882480B1 (de) |
| WO (1) | WO2006087497A2 (de) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992010401A1 (en) | 1990-12-11 | 1992-06-25 | Johnston David A | Signalling device |
| WO2009062357A1 (en) * | 2007-11-13 | 2009-05-22 | Huawei Technologies Co., Ltd. | System and method for data synchronization in passive optical networks |
| US8365050B2 (en) * | 2009-11-09 | 2013-01-29 | Research In Motion Limited | System and method for decoding a message using a priori information |
| EP3562831B1 (de) | 2016-12-29 | 2021-10-20 | Borealis AG | Katalysatoren |
| CN118677568B (zh) * | 2020-04-10 | 2025-05-02 | 华为技术有限公司 | 码字同步方法、接收器、网络设备及网络系统 |
| CN115250162A (zh) * | 2021-04-26 | 2022-10-28 | 华为技术有限公司 | 码字同步方法、接收器、网络设备及网络系统 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4404676A (en) * | 1981-03-30 | 1983-09-13 | Pioneer Electric Corporation | Partitioning method and apparatus using data-dependent boundary-marking code words |
| FR2591834B1 (fr) * | 1985-12-13 | 1988-02-19 | Radiotechnique | Procede de decodage de donnees radiodiffusees et dispositif de mise en oeuvre |
| JPH0738626B2 (ja) * | 1993-03-01 | 1995-04-26 | 日本電気株式会社 | ワード同期検出回路 |
| JP2600581B2 (ja) * | 1993-08-26 | 1997-04-16 | 日本電気株式会社 | 符号同期回路 |
| KR970004256B1 (ko) * | 1994-06-29 | 1997-03-26 | 한국전기통신공사 | 순환코드를 이용한 프레임/버스트 동기 및 에러 검출장치 |
| JPH08125640A (ja) * | 1994-10-28 | 1996-05-17 | Murata Mach Ltd | 誤り訂正符号復号器の再同期化装置 |
| JP2817638B2 (ja) * | 1994-12-06 | 1998-10-30 | 村田機械株式会社 | 誤り訂正符号復号器の再同期化装置 |
| JP2001308810A (ja) * | 2000-04-27 | 2001-11-02 | Nec Corp | マルチキャリアフレーム同期回路 |
| US7725800B2 (en) * | 2005-08-05 | 2010-05-25 | Hitachi Global Stroage Technologies Netherlands, B.V. | Decoding techniques for correcting errors using soft information |
-
2005
- 2005-02-18 FR FR0501748A patent/FR2882480B1/fr not_active Expired - Lifetime
-
2006
- 2006-02-20 WO PCT/FR2006/050145 patent/WO2006087497A2/fr not_active Ceased
- 2006-02-20 JP JP2007555674A patent/JP5214977B2/ja not_active Expired - Lifetime
- 2006-02-20 EP EP06709524A patent/EP1897264A2/de not_active Ceased
- 2006-02-20 US US11/884,562 patent/US7995692B2/en active Active
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2006087497A3 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2006087497A2 (fr) | 2006-08-24 |
| WO2006087497A3 (fr) | 2006-12-28 |
| FR2882480B1 (fr) | 2007-07-13 |
| US7995692B2 (en) | 2011-08-09 |
| US20090154623A1 (en) | 2009-06-18 |
| JP5214977B2 (ja) | 2013-06-19 |
| JP2008530933A (ja) | 2008-08-07 |
| FR2882480A1 (fr) | 2006-08-25 |
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