EP1915690A2 - Procede et dispositif pour controler des fonctions d'un systeme informatique - Google Patents

Procede et dispositif pour controler des fonctions d'un systeme informatique

Info

Publication number
EP1915690A2
EP1915690A2 EP06778027A EP06778027A EP1915690A2 EP 1915690 A2 EP1915690 A2 EP 1915690A2 EP 06778027 A EP06778027 A EP 06778027A EP 06778027 A EP06778027 A EP 06778027A EP 1915690 A2 EP1915690 A2 EP 1915690A2
Authority
EP
European Patent Office
Prior art keywords
function
functions
execution units
comparison
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06778027A
Other languages
German (de)
English (en)
Inventor
Juergen Sauler
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1915690A2 publication Critical patent/EP1915690A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • a check routine that checks if a specific component is still functional.
  • This can be z.
  • a part of the real function algorithm is calculated with default input values and then the result, which is known, is compared with a stored reference value.
  • This stored reference value can be calculated beforehand because the default input values and the algorithm are already known at the time the software was created.
  • Another type of monitoring function is realized by specifically loading output cells. This may be combined with a readback sensor values, which should then be within a certain range. There are a lot of other variations.
  • safety functions In automation technology, it is common in some places to speak of so-called safety functions. These are to be individually identified and documented in the overall application and must generally comply with the requirements of a standard (for example, IEC 61508). Even if no standard is valid, particularly high requirements for error detection are placed on these safety functions and it is not always possible to operate a monitoring function on the object to be monitored.
  • a standard for example, IEC 61508
  • Advantages of the invention are therefore that in the execution of monitoring functions whose correct and error-free (with respect to HW errors) functioning is checked with. So you can detect errors in the monitoring function. As a result, a substantially simplified safety concept is possible.
  • a monitoring in software here receives a degree of coverage of 100% with respect to errors of execution units that manifest themselves in the function at all.
  • a contextual validation of functionality is enabled. The development effort for a security concept is reduced. The overall system complexity is reduced. The concept can easily be expanded to include other security-related functions in the
  • a method for monitoring functions of a computer system having at least two execution units wherein at least two operating modes are switched and a first operating mode corresponds to a comparison mode and a second operating mode corresponds to a performance mode and a first function is monitored by a second function, characterized the second function is processed in the comparison mode on at least two execution units and each of these second functions, which are executed on at least two execution units, monitors the same first function.
  • a method is described, characterized in that the second function monitors the first function periodically.
  • a method is described, characterized in that the first function is executed in the performance mode.
  • a method is described, characterized in that results arising during the execution of the second function on the at least two execution units are compared with each other and so the second function is monitored.
  • a method is described, characterized in that the second functions on the at least two execution units are processed on the basis of context-dependent values, and resulting results are compared.
  • a method is described, characterized in that in addition to the second function, further functions are provided, which monitor other functions, wherein only a part of the other functions in the comparison mode executed on the at least two execution units and thus checked itself.
  • a device for monitoring functions of a computer system is included with at least two execution units, switching means are included and is switched between at least two operating modes and comparison means are included, wherein a first mode of operation a comparison mode and a second mode of operation corresponds to a performance mode and a first function of a second function is monitored, characterized in that the device is configured such that the second function is executed in the comparison mode on at least two execution units and each of these second functions, which are executed on at least two execution units monitors the same first function.
  • a device is advantageously included, characterized in that it is designed in such a way that results arising during the processing of the second function on the at least two execution units are compared with each other by the comparison means and thus the second function is monitored.
  • a device is advantageously included, characterized in that it is designed in such a way that the second functions on the at least two execution units are processed on the basis of context-dependent values and the resulting results are compared.
  • a device is included, characterized in that it is designed in such a way that, in addition to the second function, further functions are provided which monitor other functions, only a part of the further functions being in the comparison mode executed on the at least two execution units and thus checked itself.
  • a device is included, characterized in that the switching means and the comparison means are combined in a switching and comparison unit.
  • a device is included, characterized in that the switching and comparison unit performs the monitoring of the second function.
  • FIG. 1 describes a generalized representation of a switching and comparison unit
  • FIG. 2 describes which components are present in the arithmetic unit of the system according to the invention
  • FIG. 3 shows a subdivision of the set of functions.
  • FIG. 4 shows an alternative subdivision of the set of functions.
  • FIG. 5 shows the sequence of the decision process.
  • FIG. 6 shows a multiprocessor system with two execution units.
  • An execution unit can in the following designate both a processor / core / CPU, as well as an FPU (Floating Point Unit), DSP (Digital Signal Processor), coprocessor or ALU (Arithmetic Logical Unit).
  • the invention relates to a multiprocessor system W100 shown in FIG. 6 having at least two execution units WI 10A, WI 10B, a comparison unit W120 and a switching unit WI 50.
  • FIG. 1 describes the general case of a switching and comparison unit for more than 2 execution units.
  • the presented invention always refers to the general case with 2 or more execution units.
  • the switching unit W150 has at least two outputs to two system interfaces W130a, Wl 30b. Registers, memories or peripherals such as digital outputs, D / A converters and communication controllers can be controlled via these interfaces.
  • This multiprocessor system can be operated in at least two operating modes, a comparison mode VM and a performance mode PM. In a performance mode PM, different commands, program segments or programs are executed in parallel in the different execution units. In this operating mode, the comparison unit is deactivated.
  • the switching unit Wl 50 is configured in this operating mode such that each execution unit is connected to one of the system interfaces W130a, W130b via the optional buffer.
  • a result of an execution unit can be written into a memory W 170 or output to a peripheral component WI 80, WI 90.
  • a peripheral module can, for. Example, an analog-to-digital converter or a communication controller of a communication system (eg SPI, LIN, CAN, FlexRay).
  • SPI serial to Physical Interface
  • CAN CAN
  • FlexRay a communication controller of a communication system
  • the switching unit After a comparison, the switching unit is informed via a status signal W 125 whether it is allowed to output one of the matching results to one of the system interfaces or whether it has to block the signal due to a recognized discrepancy of the results.
  • an optional error signal Wl 55 can be output by the comparison unit.
  • This error signal can also be output by the switching unit instead of by the switching unit Wl 56.
  • the switching can be either via the execution of special switching instructions, special intervention sequences, explicitly marked instructions or by accessing a specific memory address by at least one of the execution units of the Multi-processor system are triggered.
  • n signals N140, ..., N14n go to the switching and comparison component N100. This can generate up to n output signals N160, ..., N16n from these input signals.
  • the "pure performance mode” all signals N14i are directed to the corresponding output signals N16i
  • the "pure comparison mode” all signals N140, ..., N14n only affect exactly one of the output signals N16i headed.
  • the logical component of a switching logic Nl 10 is included in this figure. This first determines how many output signals there are. Furthermore, the switching logic Nl 10 determines which of the input signals contribute to which of the output signals. An input signal can contribute to exactly one output signal. In other words, in terms of mathematical form, the circuit logic defines a function that assigns an element of the set ⁇ N160, ..., N16n ⁇ to each element of the set ⁇ N140, ..., N14n ⁇ . The processing logic N 120 then determines to each of the outputs N16i how the inputs contribute to that output signal.
  • a second possibility is to make a k out of m selection (k> m / 2). This can be realized by using comparators.
  • an error signal can be generated if one of the signals is detected as deviating.
  • a possibly different error signal can be generated if all three signals are different.
  • a third option is to apply these values to an algorithm. This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA).
  • FTA Fault Tolerant Algorithm
  • This averaging can be done over the entire set of residual values, or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. For example, averaging only adds and divides, FTM, FTA, or median require partial sorting. If necessary, an error signal can optionally also be output at sufficiently large extreme values
  • the task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal - and thus also for the associated input signals.
  • the combination of the information of the switching logic NI 10 (ie the so-called g. tion) and the processing logic (ie the determination of the comparison operation per output signal, ie per function value) is the mode information and this sets the mode.
  • this information is multivalued, ie not representable only via a logical bit. Not all theoretically conceivable modes are meaningful in a given implementation, it is preferable to limit the number of allowed modes. It should be emphasized that in the case of only two execution units, where there is only one compare mode, all the information can be condensed to only one logical bit.
  • Switching from a performance mode to a comparison mode is generally
  • Output signals N16i are switched, while they are all mapped to an output in comparison mode.
  • switching can also be realized by changing pairings. It is represented by the fact that in the general case one can not speak of the performance mode and the comparison mode, although in a given form of the invention one can restrict the set of allowed modes such that this is the case. However, one can always speak of switching from the performance to the comparison mode (and vice versa).
  • These modes can be switched over dynamically during operation, controlled by software.
  • the switching is triggered, for example, by the execution of special switching instructions, special instruction sequences, explicitly marked instructions or by the access to specific addresses by at least one of the execution units of the multiprocessor system.
  • a monitoring function is a function that checks the function or the functional capability of a component, a subsystem or an object.
  • FIG. 2 describes which components are present in the arithmetic unit of the system according to the invention.
  • the arithmetic unit O200 itself contains several execution units 0210,..., 02 In.
  • a switching and comparison unit O220 is included. This is preferably present as a component in the arithmetic unit, but it can also be distributed to various components, which may even be outside the arithmetic unit itself. It is crucial that the computing unit can supply the functions required by the switching and comparison unit, as they have been shown, for example, in the description of FIG. In addition, functions that are preferably implemented in software run on this arithmetic unit.
  • FIG. 3 shows a subdivision of the functions O230.
  • the total O300 of the functions corresponds to O230.
  • These can be subdivided into the monitoring functions O320 and other functions 0310.
  • the monitoring functions are calculated or performed in a comparison mode, while the other functions are performed in a performance mode.
  • the main advantage of this is that when executing monitoring functions, their correct and error-free (with regard to HW errors) functioning is also checked. It is also possible to detect errors in the monitoring function itself. This allows a considerably simplified safety concept. A monitoring in software is given a degree of coverage of 100% with regard to errors of execution units that manifest themselves in the function at all.
  • a further significant improvement in security is also possible by using this invention in many applications in that one calculates this monitoring function with the current context.
  • a comparison with a reference value which is known outside the components considered here, is usually necessary to determine the correctness of the monitoring function. In many cases, this can only be achieved by calculating a default value that is stored in a non-volatile memory component. This value is calculated at the time of devolution, i. not in use, and is therefore valid only for the specific context that has been accepted here.
  • an error only manifests itself in a specific context. For example, an error in a multiplication component can not always be recognized by multiplying two distinct numbers together and comparing the result to the known and stored value.
  • a monitoring function that is limited to such a default value thus has a reduced error detection.
  • Errors in the execution units is made by the switching and comparison unit.
  • FIG. 3 A variation of this idea is shown in FIG.
  • the subsets O301, 0311, 0321 correspond to O300, 0310, O320 from FIG. 3.
  • the subsets 0311 and 0321 are again divided into the quantities O350, O360 or O330, O340.
  • the underlying idea is that not all monitoring functions must run in comparison mode, but only those for which the monitoring of the execution unit is essential. These are designated O330, while the other (preferably very small) subset of monitoring functions O340, for which monitoring of the execution unit is insignificant, runs in a performance mode.
  • the subdivision of 0311 is to be understood: 0350 can be, for example, functions that directly drive a critical actuator. That is, it is also possible that some of the functions that are not monitoring functions are in a compare mode. These are summarized in O350. The remaining functions O360 run in a perfomance mode.
  • Figure 5 describes the basic decision process for the preferred case that O340 is empty and that there is only one performance and one compare mode.
  • step O400 the "sleep" state of the scheduler is taken in. As soon as the scheduler brings a process to scheduling in step 0410, the decision is made in step O420 whether it is a P-process or a V-process. If it is a V-process, it is processed in compare mode (in step O460), the scheduler then returns to its idle state (after step O400), if it is a P-process, it is next in step If this is the case, the process is processed (in step O460) in comparison mode, the scheduler then returns to its idle state
  • step O400 If not, the process is processed in performance mode (in step O440). In this case, an allocation to an execution unit must still be made in step O450. Then the scheduler returns to its idle state (O400).

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

La présente invention concerne un procédé et un dispositif pour contrôler des fonctions d'un système informatique comprenant au moins deux unités d'exécution. Des systèmes de commutation sont prévus et il est possible d'effectuer une commutation entre au moins deux modes de fonctionnement. Des systèmes de comparaison sont également prévus. Un premier mode de fonctionnement correspond à un mode comparaison et un second mode de fonctionnement correspond à un mode performance. Une première fonction est contrôlée par une seconde fonction. Dans le mode comparaison, cette seconde fonction est exécutée sur au moins deux unités d'exécution et chacune des secondes fonctions qui sont exécutées sur au moins deux unités d'exécution contrôle la même première fonction.
EP06778027A 2005-08-08 2006-07-27 Procede et dispositif pour controler des fonctions d'un systeme informatique Withdrawn EP1915690A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005037230A DE102005037230A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems
PCT/EP2006/064742 WO2007017396A2 (fr) 2005-08-08 2006-07-27 Procede et dispositif pour controler des fonctions d'un systeme informatique

Publications (1)

Publication Number Publication Date
EP1915690A2 true EP1915690A2 (fr) 2008-04-30

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EP06778027A Withdrawn EP1915690A2 (fr) 2005-08-08 2006-07-27 Procede et dispositif pour controler des fonctions d'un systeme informatique

Country Status (9)

Country Link
US (1) US8108716B2 (fr)
EP (1) EP1915690A2 (fr)
JP (1) JP2009505186A (fr)
KR (1) KR101031181B1 (fr)
CN (1) CN101243403A (fr)
DE (1) DE102005037230A1 (fr)
RU (1) RU2008108475A (fr)
TW (1) TW200736901A (fr)
WO (1) WO2007017396A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005037230A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems
EP4087195B2 (fr) 2009-09-08 2026-01-28 Abbott Diabetes Care, Inc. Procédés et articles manufacturés destinés à héberger une application critique pour la sécurité sur un dispositif de traitement de données non contrôlées
DE102011086530A1 (de) * 2010-11-19 2012-05-24 Continental Teves Ag & Co. Ohg Mikroprozessorsystem mit fehlertoleranter Architektur
CN103797489B (zh) * 2011-03-21 2017-12-12 爱迪德技术有限公司 用于安全地将程序执行绑定到且节点锁定到受信任的签名授权机构的系统和方法
JP5541246B2 (ja) * 2011-07-21 2014-07-09 株式会社デンソー 電子制御ユニット
DE102012207215A1 (de) 2012-04-30 2013-10-31 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems, vorzugsweise eines Motorsteuersystems eines Kraftfahrzeuges
KR101558280B1 (ko) 2013-09-02 2015-10-12 주식회사 팀스톤 계측 윈도우 제어 방법 및 이를 수행하는 사용자 단말
DE102013224702A1 (de) 2013-12-03 2015-06-03 Robert Bosch Gmbh Steuergerät für ein Kraftfahrzeug
DE102013227165A1 (de) * 2013-12-27 2015-07-16 Siemens Aktiengesellschaft Überwachungsvorrichtung zur Überwachung eines Schaltkreises
DE102016125240A1 (de) * 2016-12-21 2018-06-21 Endress+Hauser SE+Co. KG Elektronische Schaltung für ein Feldgerät der Automatisierungstechnik
DE102018120344B4 (de) * 2018-08-21 2024-11-21 Pilz Gmbh & Co. Kg Automatisierungssystem zur Überwachung eines sicherheitskritischen Prozesses
DE102020001561A1 (de) 2020-03-10 2021-09-16 Drägerwerk AG & Co. KGaA Medizingeräteanordnung mit einem Prüfmodul
DE102020119297A1 (de) 2020-07-22 2022-01-27 Endress+Hauser SE+Co. KG Verfahren zum Überwachen eines ersten Prozessors eines Sensormoduls durch einen zweiten Prozessor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5875195A (en) * 1997-03-31 1999-02-23 International Business Machines Corporation Method and apparatus for error injection techniques
US20050097534A1 (en) * 2003-11-01 2005-05-05 International Business Machines Corporation Method and apparatus for activating/deactivating run-time determined software routines in Java compiled bytecode applications

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233615A (en) 1991-06-06 1993-08-03 Honeywell Inc. Interrupt driven, separately clocked, fault tolerant processor synchronization
US5751932A (en) * 1992-12-17 1998-05-12 Tandem Computers Incorporated Fail-fast, fail-functional, fault-tolerant multiprocessor system
JPH08297588A (ja) 1995-04-25 1996-11-12 Fujitsu Ltd 二重照合装置
US6625749B1 (en) * 1999-12-21 2003-09-23 Intel Corporation Firmware mechanism for correcting soft errors
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US6640313B1 (en) 1999-12-21 2003-10-28 Intel Corporation Microprocessor with high-reliability operating mode
US6772368B2 (en) 2000-12-11 2004-08-03 International Business Machines Corporation Multiprocessor with pair-wise high reliability mode, and method therefore
DE10136335B4 (de) * 2001-07-26 2007-03-22 Infineon Technologies Ag Prozessor mit mehreren Rechenwerken
US7085959B2 (en) * 2002-07-03 2006-08-01 Hewlett-Packard Development Company, L.P. Method and apparatus for recovery from loss of lock step
JP2004259137A (ja) 2003-02-27 2004-09-16 Denso Corp 電子制御装置
US20070277023A1 (en) * 2003-06-24 2007-11-29 Reinhard Weiberle Method For Switching Over Between At Least Two Operating Modes Of A Processor Unit, As Well Corresponding Processor Unit
DE10349581A1 (de) * 2003-10-24 2005-05-25 Robert Bosch Gmbh Verfahren und Vorrichtung zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit
EP1807764A2 (fr) * 2004-10-25 2007-07-18 Robert Bosch Gmbh Procédé et dispositif de commutation dans un système informatique comportant au moins deux unités d'exécution
EP1812857B1 (fr) * 2004-10-25 2008-09-03 Robert Bosch Gmbh Procede et dispositif de commutation de mode dans un systeme d'ordinateur comportant au moins deux unites d'execution
KR100663864B1 (ko) * 2005-06-16 2007-01-03 엘지전자 주식회사 멀티-코어 프로세서의 프로세서 모드 제어장치 및 방법
DE102005037230A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5875195A (en) * 1997-03-31 1999-02-23 International Business Machines Corporation Method and apparatus for error injection techniques
US20050097534A1 (en) * 2003-11-01 2005-05-05 International Business Machines Corporation Method and apparatus for activating/deactivating run-time determined software routines in Java compiled bytecode applications

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2007017396A2 *

Also Published As

Publication number Publication date
US20100192021A1 (en) 2010-07-29
WO2007017396A3 (fr) 2007-10-25
KR20080032168A (ko) 2008-04-14
JP2009505186A (ja) 2009-02-05
KR101031181B1 (ko) 2011-04-26
US8108716B2 (en) 2012-01-31
DE102005037230A1 (de) 2007-02-15
WO2007017396A2 (fr) 2007-02-15
RU2008108475A (ru) 2009-09-20
TW200736901A (en) 2007-10-01
CN101243403A (zh) 2008-08-13

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