EP2013630A2 - Systèmes et procédés de transmission, modulation et amplification de puissance hf - Google Patents

Systèmes et procédés de transmission, modulation et amplification de puissance hf

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Publication number
EP2013630A2
EP2013630A2 EP07752867A EP07752867A EP2013630A2 EP 2013630 A2 EP2013630 A2 EP 2013630A2 EP 07752867 A EP07752867 A EP 07752867A EP 07752867 A EP07752867 A EP 07752867A EP 2013630 A2 EP2013630 A2 EP 2013630A2
Authority
EP
European Patent Office
Prior art keywords
signals
output
signal
phase
circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07752867A
Other languages
German (de)
English (en)
Other versions
EP2013630A4 (fr
Inventor
David F. Sorrells
Gregory S. Rawlins
Michael W. Rawlins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ParkerVision Inc
Original Assignee
ParkerVision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/508,970 external-priority patent/US7937106B2/en
Priority claimed from US11/508,989 external-priority patent/US7355470B2/en
Priority claimed from US11/509,031 external-priority patent/US8031804B2/en
Application filed by ParkerVision Inc filed Critical ParkerVision Inc
Priority to EP11181888.6A priority Critical patent/EP2405277B1/fr
Publication of EP2013630A2 publication Critical patent/EP2013630A2/fr
Publication of EP2013630A4 publication Critical patent/EP2013630A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H03F1/0272—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A by using a signal derived from the output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/429—Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21142—Output signals of a plurality of power amplifiers are parallel combined to a common output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21157—A filter circuit being added at the output of a power amplifier stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21178—Power transistors are made by coupling a plurality of single transistors in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21196—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers the supply voltage of a power amplifier being switchable controlled

Definitions

  • Power efficiency can be calculated using the relationship of the total power delivered to a load divided by the total power supplied to the amplifier. For an ideal amplifier, power efficiency is 100%. Typically, power amplifiers are divided into classes which determine the amplifier's maximum theoretical power efficiency. Power efficiency is clearly a desired characteristic of a power amplifier — particularly, in wireless communication systems where power consumption is significantly dominated by the power amplifier.
  • FIG. 15A is a block diagram that illustrates another exemplary embodiment of the Direct Cartesian 2-Branch VPA method.
  • FIG. 16 is a process flowchart embodiment for power amplification according to the Direct Cartesian 2-Branch VPA method.
  • FIG. 17 is a block diagram that illustrates an exemplary embodiment of a vector power amplifier for implementing the Direct Cartesian 2-Branch VPA method.
  • FIG. 17A is a block diagram that illustrates another exemplary embodiment of a vector power amplifier for implementing the Direct Cartesian 2-Branch VPA method.
  • FIG. 17A is a block diagram that illustrates another exemplary embodiment of a vector power amplifier for implementing the Direct Cartesian 2-Branch VPA method.
  • FIG. 39 illustrates an example time- varying complex envelope PA output signal and a corresponding envelop signal.
  • FIG. 46 illustrates another power control method.
  • FIG. 48 is a process flowchart for implementing output stage current shaping according to an embodiment of the present invention.
  • FIG. 49 is a process flowchart for implementing harmonic control according to an embodiment of the present invention.
  • FIG. 50 is a process flowchart for power amplification according to an embodiment of the present invention.
  • FIGs. 5 IA-I illustrate exemplary multiple-input single-output (MISO) output stage embodiments.
  • FIG. 52 illustrates an exemplary MISO amplifier embodiment.
  • FIG. 77 is a plot that illustrates a spectrum of magnitude to phase shift transform functions corresponding to a range of amplifier classes of operation of the
  • substantially constant envelope signals 132 and 134 are input into phase controller 130.
  • Phase controller 130 manipulates phase components of signals 132 and 134 to generate signals 146 and 148, respectively.
  • Signals 146 and 148 are substantially constant envelope signals, and are summed to generate signal 160.
  • the phasor representation associated with example 3 illustrates signals 146 and 148 as phasors Pi 46 and P 14 g, respectively.
  • Signal 160 is illustrated as phasor Pi ⁇ o- In example 3, Pi 46 is phased shifted by an angle ⁇ 3 relative to the reference signal.
  • Pi 4 s is phase shifted by an angle ⁇ 4 relative to the reference signal. ⁇ 3 and ⁇ 4 may or may not be equal.
  • Signal r(t) accordingly, is a time-varying complex envelope signal.
  • the real and imaginary phasor components of signal r(t) are also time-varying in amplitude. Accordingly, their corresponding time domain signals also have time-varying envelopes.
  • the real part phasor of the time-varying envelope signal can be obtained at any time instant by the sum of at least two substantially constant envelope components.
  • ⁇ fi of variable magnitude and phase can be constructed by the sum of four substantially constant magnitude phasor components:
  • the outputs of PAs 770, 772, 774, and 776 are coupled together to generate output signal 782 of vector power amplifier 700.
  • the outputs of PAs 770, 772, 774, and 776 are directly coupled together using a wire. Direct coupling in this manner means that there is minimal or no resistive, inductive, or capacitive isolation between the outputs of PAs 770, 772, 774, and 776. In other words, outputs of PAs 770, 772, 774, and 776, are coupled together without intervening components.
  • DAC 830 may output a single analog signal at a time.
  • a sample and hold architecture may be used to ensure proper signal timing to the four branches of the amplifier, as shown in FIG. 8 A.
  • vector power amplifier 800A substantially correspond to those described above with respect to vector power amplifier 700.
  • FIG. 8C is a block diagram that illustrates another exemplary embodiment
  • PAs 1270 and 1272 apply substantially equal power amplification to respective constant envelope signals 1264-1266.
  • the power amplification is set according to the desired output power level.
  • PA drivers and/or pre-drivers are additionally employed to provide additional power amplification capability to the amplifier.
  • PA drivers 1284 and 1286 are optionally added, respectively, between vector modulators 1260 and 1262 and subsequent PAs 1270 and 1272.
  • Respective output signals 1274 and 1276 of PAs 1270 and 1272 are substantially constant envelope signals. Further, when output signals 1274 and 1276 are summed, the resulting signal has minimal non-linear distortion. In the embodiment of FIG.
  • Output signal 1770 represents a signal having the desired I and Q characteristics of the baseband signal and the desired output power level and frequency.
  • a pull-up impedance 1778 is coupled between the output of vector power amplifier 1700 and a power supply.
  • an impedance matching network 1780 is coupled at the output of vector power amplifier 1700. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.
  • optional Autobias circuitry 1218 generates separate bias control signals 1715, 1717, and 1719, corresponding to Bias A, Bias B, and Bias C, respectively.
  • Signals 1715, 1717, and 1719 may or may not be generated separately within Autobias circuitry 1718, but are output separately as shown. Further, signals 1715, 1717, and 1719 may or may not be related as determined by the biasing required for the different stages of MISO PA 1790.
  • FIG. 18A further illustrates two different sample and hold architectures with a single or two levels of S/H circuitry as shown. The two implementations have been described above with respect to FIG. 18.
  • Other aspects of vector power amplifier 1800A are substantially equivalent to those described above with respect to vector power amplifiers 1700 and 1800.
  • Step 2130 includes calculating a magnitude
  • is such that
  • 2
  • steps 2120 and 2130 are performed by I and Q Data Transfer Function module 1216 based on received information signal 1210.
  • Step 2140 includes normalizing the measured
  • are normalized to generate an Iclk_phase and Qclk_phase signals (as shown in FIG. 10) such that
  • 2 constant.
  • step 2140 is performed by I and Q Data Transfer Function module 1216 based on received information signal 1210.
  • component 2240 normalizes the measured
  • phase shift angle ⁇ between first and second constant envelope constituents.
  • component 2050 uses the calculated phase shift angle ⁇ , component 2050 then calculates in-phase and quadrature amplitude information associated with the first and second constant envelope constituents.
  • phase shift angle ⁇ (t) can be written as a function of R(t) as follows:
  • FIG. 78 illustrates a mathematical derivation of the magnitude to phase shift transform in the presence of amplitude and phase errors in branches of the VPA. Equation (28) in FIG. 78 takes into account both phase and amplitude errors in an exemplary embodiment. Note that R*sin( ⁇ *t + ⁇ ) in FIG. 78 can be representative of either /J 1 or R 2 in FIG. 25, for example. Equation (28) assumes that amplitudes Al and A2 of the VPA branches can be different and that each branch can contain a respective phase error ⁇ el(t) and ⁇ pe2(t).
  • Output stage embodiment 3300 may also include pull-up impedances 3125- ⁇ 1,..., n ⁇ , 3135- ⁇ 1,..., n ⁇ , and 3145 coupled at the output of each power amplification stage to achieve a proper biasing of that stage. Additionally, output stage embodiment 3300 may include matching impedances 3210- ⁇ 1,..., n ⁇ , 3220- ⁇ l,..., n ⁇ , and 3240 coupled at the output of each power amplification stage to maximize power transfer from that stage. Further, output stage embodiment 3300 receives an autobias signal 3310, from an Autobias module 3340, coupled at the PA stage input of each PA branch 3305- ⁇ l,..., n ⁇ .
  • embodiments of the present invention may be implemented using pnp BJTs, CMOS, NMOS, PMOS, or other type of transistors. Further, embodiments can be implemented using GaAs and/or SiGe transistors with the desired transistor switching speed being a factor to consider.
  • FIG. 5 ID Two-input single-output embodiments of FIG. 5 ID can be further extended to create multiple-input single-output PA embodiments.
  • FIG. 5 IE illustrates various embodiments of multiple-input single-output PAs according to embodiments of the present invention.
  • bias control may be provided to each of the pre- driver, driver, and/or PA stages of each branch of the PA embodiment. Bias control may be provided to one or more the stages based on the specific implementation of that stage. Further, bias control may be required for certain implementations, while it can be optionally employed in others.
  • output stage current control functions are employed to increase the output stage efficiency of a vector power amplifier (VPA) embodiment
  • output stage current control is used to provide output stage protection from excessive voltages and currents which is further describe in section 3.5.3.
  • output stage current control functions are performed using the Autobias module described above with reference to FIG. 33. A description of the operation of the Autobias module in performing these current control functions is also presented below according to an embodiment of the present invention.
  • Step 4920 includes coupling a plurality of impedances between the first ports of the plurality of transistors and a bias signal.
  • step 4920 is achieved by coupling impedances Zl,..., Z8 between base terminals of respective transistors Ql,..., Q8 and Iref signal.
  • values of the plurality of impedances are selected to cause a time-staggered switching of the input signal, thereby harmonically shaping an output signal of the PA stage.
  • a multi-stage staggered output may be generated by selecting multiple distinct values of the plurality of impedances.
  • switching is achieved by selecting the plurality of impedances to have equal or substantially equal value.
  • frequency band allocation on lower and upper spectrum bands for various communication standards is provided in FIG. 53.
  • the DCS 1800 (Digital Cellular System 1800) and the PCS 1900 (Personal Communications Service 1900) bands can support different GSM-based implementations, also known as GSM-1800 and GSM-1900.
  • the 3G TDD bands are allocated for third generation time division duplex standards such as UMTS TDD (Universal Mobile Telephone System) and TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) , for example.
  • the 3G FDD bands are allocated for third generation frequency division duplex standards such as WCDMA (Wideband CDMA), for example.
  • State machine 5606 performs various functions related to the signal generation and/or performance monitoring functions of digital control module 5600.
  • state machine 5606 includes a transfer function module, as described in Section 3, for performing signal generation functions.
  • state machine 5606 includes modules for generating, among other types of signals, bias control signals, power control signals, gain control signals, and phase control signals.
  • state machine 5606 includes modules for performing error pre-compensation in a feedforward error correction system.
  • RAM 5608 and/or NVRAM 5610 are optional components of digital control module 5600.
  • memory (RAM 5608, NVRAM 5610) bits of the digital control module 5700 can be programmed to indicate the standard to be used (e.g., WCDMA, EDGE, GSM, etc.) for communication. Programming of digital control module 5700 is done using digital I/O bus 5704.
  • control signal 5790 is an optional control signal which may be used to dynamically change the response of interpolation filters in the analog core of the VPA. This may be needed as the interpolation filters have different optimal responses for different communication standards. For example, the optimal filter response has a 3 dB corner frequency around 5 MHz for WCDMA or EDGE, while this frequency is around 400 KHz for GSM. Accordingly, control signal 5790 allows for optimizing the interpolation filters according to the used communication standard.
  • FIG. 58 illustrates another exemplary digital control module 5800 according to an embodiment of the present invention.
  • Exemplary digital control module 5800 is similar in many respects to digital control module 5700.
  • both embodiments 5700, 5800 have the same input interface 5602, and substantial portions of the output interface (the output interface in FIG. 58 is labeled with reference number 5604').
  • the differences between exemplary embodiments 5700 and 5800 relate to the type of feedback information being provided to the digital control module.
  • the two embodiments 5700 and 5800 are designed to operate with distinctly different feedback mechanisms for error correction. These mechanisms will be further described below in Section 4.3 with reference to the exemplary analog core implementations.
  • vector modulators 5922, 5924 or 5926 the operation of vector modulators 5922, 5924 or 5926,
  • MA VSUPPLY signal 6006, MA Driver VSUPPLY signal 6004, and MA Output Stage VSUPPLY signal 6002 correspond respectively to signals 5903, 5907, and 5911 in FIG. 59.
  • MA INl and MA IN2 input signals 6008 and 6010 and MA Output signals 6046, 6048, and 6050 correspond respectively to MISO input signals 5939 and 5941 and output signals 5954, 5956, and 5958 in FIG. 59.
  • PWR Detect signal 6023 corresponds to PWR Detect A signal 5938 in FIG. 59. (Generally, implementation of MISO amplifier 5932 could also be based on MISO amplifier stage 6058 in FIG.
  • embodiments of the present invention provide a variety of VPA designs encompassing a wide range of cost and performance options.
  • the output stage of analog core 6100 receives optional bias control signals from digital control module 5700. These are output stage autobias signal 5761, driver stage autobias signal 5763, and gain balance control signal 5749, which have been described above with reference to analog core 5900.
  • PWR Detect signals 6152, 6154, 6156, 6158, and 6160 are summed together, in an embodiment, using summer 5952, to generate a signal that corresponds to the current output power of the VPA.
  • MISO amplifiers 6126, 6128, 6130, 6132 and/or 6134 shown in FIG. 61 can be implemented using an amplifier such as MISO amplifier stage 6220.
  • Output stage embodiment 6200 is substantially similar to output stage embodiment 6000 illustrated in FIG. 60, with the main difference being in the elimination of the output switching stage (embodied by switch 6044 in FIG. 60) in embodiment 6200.
  • MISO amplifier stage 6434 is fabricated using SiGe, and the output switching stage 6420 is fabricated using GaAs.
  • PA stage (PAs 6414 and 6416) of MISO amplifier stage 6434 and the output switching stage 6420 are fabricated using GaAs, while other circuitry of MISO amplifier stage 6434 and optional circuitry of the output stage are fabricated using SiGe.
  • the outermost, central, and innermost regions define the type of power control to be applied according to the power level of the output waveform. For example, referring to FIG. 67, at lower power levels (points falling in the innermost region), bias control and amplitude control are used to provide the required waveform linearity. On the other hand, at higher power levels (points falling in the outermost region), phase control (by controlling the outphasing angle) only is sufficient.
  • the transfer function module receives I and Q data and generates amplitude information that is used by the vector modulators to generate substantially constant envelope signals.
  • the substantially constant envelope signals are amplified and summed in a single operation using the MISO amplifier output stage.
  • Step 130 includes controlling the power amplifier to operate according to the determined amplifier class of operation.
  • the power amplifier is controlled using phase control, bias control, and/or amplitude control methods, as described herein.
  • VPA output stage When the VPA output stage operates as a class S amplifier, it effectuates Pulse

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)

Abstract

L'invention concerne des procédés et des systèmes d'amplification de puissance à combinaison de vecteurs. Dans un premier mode de réalisation, une pluralité de signaux sont amplifiés individuellement, puis sommés afin de former un signal souhaité d'enveloppe complexe variant dans le temps. Les caractéristiques de phase et/ou de fréquence de l'un ou de plusieurs des signaux sont commandées pour fournir des caractéristiques de phase, de fréquence et/ou d'amplitude souhaitées du signal souhaité d'enveloppe complexe variant dans le temps. Dans un autre mode de réalisation, un signal d'enveloppe complexe variant dans le temps est décomposé en une pluralité de signaux constitutifs à enveloppe constante. Les signaux constitutifs sont amplifiés de manière égale ou sensiblement égale puis sont sommés afin de construire une version amplifiée du signal originel d'enveloppe variant dans le temps. Des modes de réalisation effectuent également une transposition de fréquence.
EP07752867A 2006-04-24 2007-03-12 Systèmes et procédés de transmission, modulation et amplification de puissance hf Withdrawn EP2013630A4 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP11181888.6A EP2405277B1 (fr) 2006-04-24 2007-03-12 Systèmes et procédés de transmission de puissance RF, modulation et amplification

Applications Claiming Priority (7)

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US79412106P 2006-04-24 2006-04-24
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US79870506P 2006-05-09 2006-05-09
US11/508,970 US7937106B2 (en) 2006-04-24 2006-08-24 Systems and methods of RF power transmission, modulation, and amplification, including architectural embodiments of same
US11/508,989 US7355470B2 (en) 2006-04-24 2006-08-24 Systems and methods of RF power transmission, modulation, and amplification, including embodiments for amplifier class transitioning
US11/509,031 US8031804B2 (en) 2006-04-24 2006-08-24 Systems and methods of RF tower transmission, modulation, and amplification, including embodiments for compensating for waveform distortion
PCT/US2007/006197 WO2007133323A2 (fr) 2006-04-24 2007-03-12 Systèmes et procédés de transmission, modulation et amplification de puissance hf

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111505474A (zh) * 2020-04-24 2020-08-07 中国科学院长春光学精密机械与物理研究所 Co2激光放大器的上能级寿命测试装置及方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100992331B1 (ko) * 2008-08-12 2010-11-05 삼성전기주식회사 고주파 변조기용 부스터 증폭회로 및 고주파 변조기
US9679869B2 (en) 2011-09-02 2017-06-13 Skyworks Solutions, Inc. Transmission line for high performance radio frequency applications
KR102250612B1 (ko) 2012-06-14 2021-05-10 스카이워크스 솔루션즈, 인코포레이티드 고조파 종단 회로를 포함하는 전력 증폭기 모듈 및 관련된 시스템, 장치, 및 방법
CN104508975B (zh) 2012-06-14 2018-02-16 天工方案公司 工艺补偿的hbt功率放大器偏置电路和方法
JP2016127577A (ja) 2015-01-08 2016-07-11 富士通株式会社 歪補償装置及び歪補償方法
US9577656B2 (en) * 2015-02-19 2017-02-21 Biosense Webster (Israel) Ltd. Narrowband analog noise cancellation
US10128803B2 (en) * 2016-04-22 2018-11-13 Cirrus Logic, Inc. Systems and methods for predictive switching in audio amplifiers
DE112017007378T5 (de) * 2017-03-30 2019-12-12 Intel Corporation Verteiltes Feed-Forward-Hüllkurvenverfolgungssystem
US10998867B2 (en) * 2019-05-29 2021-05-04 Cirrus Logic, Inc. Avoiding clipping in audio power delivery by predicting available power supply energy
US11381266B1 (en) * 2020-12-31 2022-07-05 Iridium Satellite Llc Wireless communication with interference mitigation

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2758682B2 (ja) * 1990-02-07 1998-05-28 富士通株式会社 定振幅波合成形増幅器
US5287069A (en) * 1990-02-07 1994-02-15 Fujitsu Limited Constant-amplitude wave combination type amplifier
JPH0495409A (ja) * 1990-08-13 1992-03-27 Fujitsu Ltd 増幅器
JPH0537263A (ja) * 1991-07-30 1993-02-12 Fujitsu Ltd 定振幅波合成形増幅器
US5365187A (en) * 1993-10-29 1994-11-15 Hewlett-Packard Company Power amplifier utilizing the vector addition of two constant envelope carriers
JPH08163189A (ja) * 1994-12-06 1996-06-21 Nec Corp 送信回路
US5541554A (en) * 1995-03-06 1996-07-30 Motorola, Inc. Multi-mode power amplifier
US5990734A (en) * 1998-06-19 1999-11-23 Datum Telegraphic Inc. System and methods for stimulating and training a power amplifier during non-transmission events
US6043707A (en) * 1999-01-07 2000-03-28 Motorola, Inc. Method and apparatus for operating a radio-frequency power amplifier as a variable-class linear amplifier
US6559722B1 (en) * 1999-08-10 2003-05-06 Anadigics, Inc. Low bias current/temperature compensation current mirror for linear power amplifier
JP2003298361A (ja) * 2002-03-29 2003-10-17 Shimada Phys & Chem Ind Co Ltd 電力増幅方法および電力増幅器
KR100473811B1 (ko) 2003-02-21 2005-03-10 학교법인 포항공과대학교 링크 전력 송신기
JP4111003B2 (ja) * 2003-02-27 2008-07-02 住友電気工業株式会社 Ｌｉｎｃ方式線形増幅器
JP4202852B2 (ja) * 2003-08-27 2008-12-24 株式会社ルネサステクノロジ 通信用電子部品および送受信切替え用半導体装置
JP3910167B2 (ja) * 2003-09-25 2007-04-25 松下電器産業株式会社 増幅回路
US6970040B1 (en) * 2003-11-13 2005-11-29 Rf Micro Devices, Inc. Multi-mode/multi-band power amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111505474A (zh) * 2020-04-24 2020-08-07 中国科学院长春光学精密机械与物理研究所 Co2激光放大器的上能级寿命测试装置及方法
CN111505474B (zh) * 2020-04-24 2021-11-02 中国科学院长春光学精密机械与物理研究所 Co2激光放大器的上能级寿命测试装置及方法

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JP5232773B2 (ja) 2013-07-10
EP2405277A3 (fr) 2012-04-18
EP2405277A2 (fr) 2012-01-11
EP2013630A4 (fr) 2009-08-12
KR101411050B1 (ko) 2014-06-25
WO2007133323A3 (fr) 2008-05-22
KR101383480B1 (ko) 2014-04-14
JP5486068B2 (ja) 2014-05-07
CA2650532A1 (fr) 2007-11-22
KR20090013803A (ko) 2009-02-05
KR20130102127A (ko) 2013-09-16
KR101411170B1 (ko) 2014-06-23
JP2009534988A (ja) 2009-09-24
ES2492680T3 (es) 2014-09-10
KR20130102128A (ko) 2013-09-16
CA2650532C (fr) 2014-06-17
JP2013059079A (ja) 2013-03-28
EP2405277B1 (fr) 2014-05-14

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