Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
  • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
  • G06F7/723—Modular exponentiation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
  • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
  • G06F7/724—Finite field arithmetic
  • G06F7/725—Finite field arithmetic over elliptic curves
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
  • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
  • H04L9/302—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
  • H04L9/3066—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy involving algebraic varieties, e.g. elliptic or hyper-elliptic curves
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
  • G06F2207/7219—Countermeasures against side channel or fault attacks

Definitions

• the present invention relates to a countermeasure method in an electronic component implementing an asymmetric cryptography algorithm with a private key, resistant to attacks aimed at discovering the private key. It also relates to a microcircuit device and a portable device, in particular a smart card, implementing such a method.
• an asymmetric cryptographic algorithm application 10 involving the use of a private key d is generally implemented by a microcircuit 12 to authenticate the transmission of a message M by a signature of this message. message or to protect the reception of an encrypted message M by a decryption of this message, using the private key.
• the private key d is for example stored in the microcircuit 12 which includes a memory 14 including itself a secure memory space 16 provided for this purpose and a microprocessor 18 for executing the asymmetric cryptographic algorithm 10.
• Microcircuit devices implementing cryptographic algorithms are sometimes attacked to determine the secret data they manipulate such as the key (s) used and possibly, in some cases, information on the messages. themselves.
• asymmetric cryptography algorithms are under attack to discover the private key, when it is used.
• Auxiliary channel attacks are an important family of cryptanalysis techniques that exploit certain properties of software or hardware implementations of cryptographic algorithms.
• the attacks of the SPA (Simple Power Analysis) or DPA (Differential Power Analysis) type consist in measuring the incoming and outgoing currents and voltages in the microcircuit. during the execution of the asymmetric cryptographic algorithm in order to deduce the private key. The feasibility of this family of attacks has been demonstrated in the article by P. Kocher, J.
• Fault injection (s) attacks are also known, among which are the DFA (Differential Fault Analysis) attacks, which consist in intentionally generating faults during the execution of the algorithm. cryptography, for example by disrupting the microcircuit on which it runs. Such a disturbance may include one or more short illumination (s) of the microcircuit or the generation of one or more peak (s) of voltage on one of its contacts. It thus makes it possible, under certain conditions, to exploit the calculation and behavior errors generated in order to obtain part or all of the private key sought.
• DFA Different Fault Analysis attacks
• RSA asymmetric cryptographic algorithm
• An efficient implementation of this primitive uses a binary representation of the private key d by iterating on each bit of this binary representation. In each iteration, the calculation performed and in fact the energy consumption during the calculation depends on the value of the bit concerned. Therefore, the execution of such a primitive makes the private key particularly vulnerable to the aforementioned attacks.
• a primitive consisting of a scalar multiplication is executed.
• This primitive uses a binary representation of the private key d by iterating on each bit of this binary representation. Similarly, in each iteration, the energy consumption during the calculation depends on the value of the bit concerned. Therefore, the execution of such a primitive also makes the value of the scalar, which can be assimilated for security reasons to a private key, particularly vulnerable to attack. In order to combat these attacks which are varied by nature, many solutions very different from each other have been made.
• the invention more particularly relates to those which implement a method of countermeasure in an electronic component implementing a private key asymmetric cryptography algorithm, comprising the steps of:
• the protection parameter a is conventionally generated using a pseudo-random data generator 20, so that the execution of the primitive by the cryptographic algorithm 10 is itself made random and decorrelated of the private key used, for example by a technique commonly referred to as masking, which can also be renamed a method of transformation or deformation of the data since their manipulation is deformed as opposed to their raw use, carried out by a countermeasure section 22 of the microprocessor 18, using the protection parameter a.
• the intermediate data of the cryptographic algorithm and, consequently, the measurable currents are modified by the random protection parameter and their observation does not make it possible to find the true value of the private key.
• the masking does not disturb the algorithm itself, which therefore provides the same result with or without masking.
• Another embodiment of an attack-resistant RSA algorithm comprises a first step in which the protection parameter d1 is chosen randomly such that 0 ⁇ d1 ⁇ d.
• the private key d is decomposed into at least two exponents d1 and d2 of sizes comparable to that of d, so that the RSA algorithm is complicated by imposing on the at least two executions of the modular exponentiation instead of one.
• One embodiment of the invention relates to a countermeasure method in an electronic component implementing a private key asymmetric cryptography algorithm, comprising the steps of:
• the protection parameter is used to transform the binary blocks rather than the complete binary representation of the private key. Consequently, the size of the binary representation of the protection parameter can be much smaller than that of the binary representation of the private key, that is to say of the order of that of the binary blocks.
• We simplify the calculation because, even if we increase the number of executions of the primitive, they operate on binary data of smaller sizes. At the end of the day, we can protect the execution of the algorithm asymmetric cryptography by significantly reducing its complexity compared to conventional countermeasure methods.
• the countermeasure method comprises the step of dividing the binary representation of the private key such that the size of each binary block is greater than or equal to that of the binary representation of the protection parameter. .
• the countermeasure method comprises the step of dividing the binary representation of the private key into a plurality of bit blocks such that the sum of the sizes of the binary blocks is equal to the size of the binary representation. of the private key.
• the countermeasure method comprises the step of randomly determining iteratively the size of each bit block so that the value of each bit block is greater than the value of the protection parameter. According to one embodiment, the countermeasure method comprises the steps of:
• the primitive is a modular exponentiation of the input data by the private key for the realization of an RSA or RSA CRT type cryptographic algorithm.
• the countermeasure method comprises a preliminary step of masking the RSA module and the input data.
• the primitive is a scalar multiplication of the input data by the private key, for the realization of a cryptography algorithm based on an elliptic curve in which the input data is a predetermined point of the elliptic curve.
• the countermeasure method comprises a preliminary step of masking the predetermined point of the elliptical curve. According to one embodiment, the countermeasure method further comprises the steps of: initially generating, in a reproducible manner, at least one verification parameter before any execution of the primitive,
• the regeneration and comparison step is performed at each iteration of the primitive when it is applied to a transformed binary block.
• the countermeasure method comprises the step of triggering an alert and scrambling at least the private key, if the regeneration and comparison step indicates a difference between the verification parameter initially generated and the regenerated verification parameter.
• the generation of the protection parameter and / or the verification parameter comprises the steps of:
• the countermeasure method comprises the steps of: defining a plurality of functions, each function being generator, by successive applications to at least one predetermined secret parameter and stored in memory, of a sequence of corresponding values determinable only from the corresponding secret parameter and the corresponding function, - combining the plurality of sequences of values generated using a predefined relation to generate a new sequence of values,
• the countermeasure method comprises the steps of: define a generating function, by successive applications to at least one predetermined secret parameter stored in memory, of a sequence of values that can be determined solely from the secret parameter and from the function; combining the sequence of generated values with public parameters the cryptographic algorithm to generate a new sequence of values,
• Another embodiment of the invention consists in providing a microcircuit device, comprising a microprocessor for implementing a countermeasure method of a private key asymmetric cryptography algorithm, at least one secure memory for storage of the private key, and a data generator for generating a protection parameter, characterized in that it is configured to:
• the microprocessor is configured to iteratively randomly determine the size of each bit block such that the value of each bit block is greater than the value of the protection parameter.
• the primitive is a modular exponentiation of the input data by the private key for the realization of an RSA or RSA CRT type cryptographic algorithm.
• the primitive is a scalar multiplication of the input data by the private key, for the realization of a cryptography algorithm based on an elliptic curve in which the input data is a predetermined point of the elliptic curve.
• the microcircuit device is configured to further initially reproducibly generate at least one verification parameter before any execution of the primitive, to regenerate this verification parameter during execution or after execution of the primitive and compare the regenerated verification parameter with the verification parameter initially generated.
• the data generator is configured to generate the protection parameter and / or the verification parameter in:
• the data generator is configured to:
• each function being generating, by successive applications to at least one predetermined secret parameter and stored in memory, a corresponding sequence of values that can be determined solely from the corresponding secret parameter and the corresponding function
• the data generator is configured to: define a generating function, by successive applications to at least one predetermined secret parameter stored in memory, of a sequence of values that can be determined solely from the secret parameter and from the function; combining the sequence of generated values with public parameters the cryptographic algorithm to generate a new sequence of values,
• Another embodiment of the invention consists in providing a portable device, in particular a smart card, comprising a microcircuit device as described above.
• FIG. 1 previously described schematically represents the structure of a microcircuit device, of conventional type
• FIG. 2 schematically represents the structure of a microcircuit device, according to a first embodiment of the invention.
• FIG. 3 schematically represents a smart card comprising the device of FIG. 2,
• FIG. 4 illustrates the successive steps of a first countermeasure method implemented by the device of FIG. 2,
• FIG. 5 illustrates the successive steps of a second countermeasure method implemented by the device of FIG. 2,
• FIG. 6 illustrates the successive steps of a third countermeasure method implemented by the device of FIG. 2
• FIG. 7 illustrates the successive steps of a fourth countermeasure method implemented by the device of Figure 2
• FIG. 8 illustrates the successive steps of a fifth countermeasure method implemented by the device of FIG. 2,
• FIG. 9 schematically represents the structure of a microcircuit device, according to a second embodiment of the invention
• FIG. 10 illustrates the successive steps of a countermeasure method implemented by the device of FIG. 9.
• the microcircuit device 12 'represented in FIG. 2 comprises, like that represented in FIG. 1, an algorithmic application of asymmetric cryptography 10, a memory 14 including a secure memory space 16 for storing, in particular, a private key d for use by the application 10, a microprocessor 18 and a pseudo random data generator 20 for providing a protection parameter a. It also has a countermeasure section 22 ', but this provides an improvement to the existing countermeasures, in particular to the countermeasure section 22 previously described.
• the device 12 ' is for example integrated in a portable device, in particular in the form of a secure smart card chip 30, as shown in FIG.
• the countermeasure section 22' comprises:
• d bin [D ⁇ 1 , ..., D 0 I 2 , and
• the generator 20 may be designed to generate a protection parameter a whose size of the binary representation is at most equal to half the size of the binary representation of the private key d.
• the section 22'a can be designed to divide the binary representation of the private key so that the size of each binary block is greater than or equal to that of the binary representation of the parameter of protection.
• the algorithmic application of asymmetric cryptography 10 then executes the primitive using data whose size does not exceed half that of d b ⁇ n . The gain in calculation time is very sensitive.
• FIG. 4 A first method of this type, performing an N-type RSA type cryptography on a message M, is illustrated in FIG. 4.
• a verification parameter r1 is generated.
• This verification parameter r1 is for example determined by the application of a predetermined COMB function, combining in particular a value v generated by the generator 20 and stored in memory, the protection parameter a and other parameters of the RSA algorithm. .
• the message M and the module RSA N can also be transformed using functions g and h:
• N N ⁇ - h (N)
• M M ⁇ - g (M) mod N
• V Exp (M, a, N, V), where V represents an intermediate data calculated using the Exp primitive from the input data M and the protection parameter a.
• the output data S is initialized to 1 and a counter i to n-1. Then, during a test step 108, the value of the counter i is tested.
• this value is strictly positive, it goes to a step 110, if not to an optional step 120 followed by a final step 122 or directly to the final step 122.
• an integer j is determined, for example randomly, which verifies the following conditions:
• This value D represents a binary block of the private key d transformed by a.
• S Exp (M, D, N, S).
• V the intermediate value V is combined with the value of S obtained in step 114, as follows: S ⁇ - SV mod N.
• step 120 which is optional, follows step 108 when the value of the counter i is null and as long as the optional step 102 has been performed.
• the parameter r1 is calculated again, using the COMB function and the public and / or stored values used by this function. If the value of r1 has changed between step 102 and step 120, it can be concluded that a fault injection attack (s) has occurred between these two steps.
• An alert is then transmitted by the cryptographic application 10.
• the output data S 1 is also unmasked as a function of the functions g and h that have been used to mask the input data M.
• the reverse transformation (unmasking) performed with a fault makes it possible to counter an attack by fault injection (s).
• the cryptographic application 10 returns the value S.
• Steps 200, 202 (optional) and 204 of this second method remain identical to steps 100, 102 (optional) and 104 previously described.
• the output data S is initialized to 1 and a counter i to u-1.
• C [C ⁇ 1 C 0 ] 2 , recursively calculated as follows:
• D ' represents the ith binary block of the private key d transformed by a.
• step 214 the intermediate value V is combined with the value of S obtained in step 212, as follows:
• Steps 218 and 220 are identical to steps 120 and 122 previously described.
• RSA CRT type cryptography ie RSA algorithm using the Chinese Remainder Theorem
• the RSA CRT algorithm is an alternative to the RSA algorithm for performing a signature or decryption: it is four times faster. It defines the following parameters:
• steps 300 and 302 (optional) of this third method remain identical to the steps 100, 200 and 102, 202 (optional) previously described.
• Vp Exp (M, a, p, Vp), where Vp represents an intermediate data computed using the Exp primitive from the input data M and the protection parameter a.
• Vq Exp (M, a, q, Vq), where Vq is an intermediate data calculated using the Exp primitive from input data M and protection parameter a.
• steps 304 to 310 are executed is not fixed. Indeed, it is important only that they be executed after step 302, that step 304 is executed before step 306 and that step 308 is executed before step 310.
• an optional step 312 is followed by a final step 314 or directly at the final step 314.
• the optional step 312 is identical to the step 120 and is performed only if the optional step 302 has been executed.
• the cryptographic application 10 calculates the value of S from S p and S q as previously indicated and returns this value.
• a fourth countermeasure method according to the invention that can be implemented by the device of FIG. 2, performing an Elliptic Curve type cryptography on a message M, will now be presented with reference to FIG.
• an elliptic curve asymmetric cryptography algorithm otherwise known as the Elliptic Curve Cryptosystem (ECC) algorithm
• ECC Elliptic Curve Cryptosystem
• a verification parameter r is generated.
• This verification parameter r is for example determined by the application of a predetermined COMB function, combining in particular a value v generated by the generator 20 and stored in memory, the protection parameter a and other parameters of the ECC algorithm. .
• V ScalarMult (P, a, V), where V represents an intermediate data computed using the ScalarMult primitive from the input data P and the protection parameter a.
• the output data Q is initialized to 0 and a counter i to n-1.
• step 408 the value of the counter i is tested. If this value is strictly positive, proceed to a step 410, if not to an optional step 420 followed by a final step 422 or directly to the final step 422.
• step 410 an integer j is determined by example randomly, which verifies the following conditions:
• step 416 the intermediate value V is combined with the value of Q obtained in step 414, as follows: Q + - Q + V.
• Step 420 which is optional, follows step 408 when the value of counter i is zero and provided that optional step 402 has been performed.
• the parameter r is calculated again, using the function COMB and the public values and / or stored in memory used by this function. If the value of ra changed between step 402 and step 420, it can be concluded that a fault injection attack (s) occurred between these two steps.
• An alert is then sent by the application of cryptography 10.
• step 420 the output data Q is also unmasked, as a function of the function g which has been used to mask the input data P. According to the alert transmitted by the application cryptography 10, the inverse transformation (unmasking) performed with a fault makes it possible to counter an attack by fault injection (s).
• the fourth method described above involves n + k scalar multiplication iterations: k iterations during step 404 and n iterations in the loop of steps 408 to 418.
• the extra cost of the countermeasure on the ECC algorithm is very small. In any case, it is much weaker than that of prior art solutions involving at least 2 n scalar multiplication iterations.
• V ScalarMult (-P, a, V).
• D d
• FIG. 8 A fifth countermeasure method according to the invention that can be implemented by the device of FIG. 2, and also performing Elliptic Curve cryptography, is illustrated in FIG. 8. It is a variant of FIG.
• Steps 500, 502 (optional) and 504 of this fifth method remain identical to steps 400, 402 (optional) and 404 previously described.
• the output data Q is initialized to 0 and a counter i to u-1.
• step 508 the value of the counter i is tested. If this value is strictly positive, proceed to a step 510, if not to an optional step 518 followed by a final step 520 or directly to the final step 520.
• D ⁇ D
• D ⁇ D
• step 514 the intermediate value V is combined with the value of Q obtained in step 512, as follows:
• Steps 518 and 520 are identical to steps 420 and 422 previously described.
• V ScalarMult (-P, a, V).
• V ScalarMult (-P, a, V).
• the microcircuit device 12 "represented in FIG. 9 comprises, like that represented in FIG. 2, an algorithmic application of cryptography 10, a memory 14 including a secure memory space 16, a microprocessor 18 and a countermeasure section 22 '. It is for example integrated in a portable device, in particular in the form of a chip of a secure smart card 30 as shown in FIG. 3. It will be noted, however, that although the algorithmic application of cryptography 10 and the section of against Measurements 22 'have been represented as distinct, these can in fact be intimately nested in the same implementation of a cryptography algorithm including a countermeasure.
• the countermeasure section 22 'of the device 12 “comprises, like that of the device 12':
• a section 22'b for transforming each binary block D 1 by means of a protection parameter a and, for each converted binary block D ',, to perform an intermediate calculation using the primitive.
• the pseudo-random data generator 20 of the conventional type is replaced by a data generator 20" which comprises: a section 20 "a of application of a function F predefined to at minus a predetermined secret parameter S for the generation of a determinable sequence of values only from this secret parameter and this function F, and
• a section 20 "b for providing at least one protection parameter reproducibly has a value of this sequence.
• Section 20 is actually a software or hardware implementation of the F function.
• the secret parameter S is stored in the secure memory 16 and supplied at the input of the section 20 "of the generator 20", while the protection parameter a is provided, at the output of the section 20 “b, at the counter section. -measure 22 '.
• the parameter a is not therefore a hazard in the conventional sense mentioned in the documents of the state of the art.
• This is a deterministic result derived from the calculation of the function F executed by the generator 20 "over at least one secret parameter S which may be specific to the smart card 30 on which the microcircuit 12 'is arranged.
• This secret parameter is for example derived from a public datum of the device 30.
• the element A n can be processed before providing the parameter a.
• sequence (A n ) is cyclic and / or operates in a finite set of elements, the space of the values A n generated will have to be large enough to resist the attacks. In fact, the greater the space considered, the better the robustness of the countermeasure.
• sequences of values (A n ) that can be provided by a generator 20 "according to the second embodiment of the invention .Then a second step, we will expose several possible uses of such sequences of values for the provision of protection parameters in particular to the five countermeasure applications in asymmetric cryptography previously described with reference to FIGS. 4 to 8.
• this sequence takes the form of the group of inverse affine transformations on the finite field
• GF (m) ⁇ 0, 1 m-1 ⁇ .
• m is one of the secret parameters to be kept in the secure memory of the device.
• the initial element A 0 is chosen as being the generating element a to which the law of internal composition of the group GC is applied k times,
• the secret parameters S used by the generating function of the sequence (A n ) are then, for example, the generating element a and the values k, k 'and m.
• the protection parameters generated are for example the elements of the sequence (A n ).
• Frobenius groups An interesting property of Frobenius groups is that no non-trivial element fixes more than one point.
• a secret parameter A 0 for example 16 bits
• a corresponding CRC polynomial among those conventionally used in CRC calculations, for example the CRC-16 polynomial (X 16 + X 15 + X 2 + 1) or the CRC CCITT V41 polynomial (X 16 + X 12 + X 5 + 1).
• the function T in question can be a secret matrix of values, the values A ' n and A " n respectively denoting respectively a row and a column of this matrix.
• the sequence (A n ) can be generated from a first sequence (A ' n ), also according to public data, such as for example data used during the execution of the cryptography application with countermeasure and not secret. Among these data, depending on the applications, mention may be made of the message M (in clear or encrypted), a public key e, etc.
• the values of the sequence used as protection parameters are then calculated using any COMB function combining all these data:
• a n COMB (A ' n , M, e, ).
• FIG. 10 illustrates an example of steps performed by a method according to the second embodiment of FIG. 9, applied to the execution of an asymmetric cryptographic algorithm with countermeasure, using T protection parameters a ,,. .. a ⁇ by execution, all the protection parameters can be extracted from the same sequence of values (A n ) generated by the section 20'a.
• a counter i is initialized to 0. This counter i is intended to keep in memory the number of times that the asymmetric cryptographic algorithm has been executed since this step of initialization INIT, as long as another initialization is not performed.
• the secret parameter S (or the parameters S when there are several), from which the sequence of values must be generated, is defined. It can be kept from a previous initialization, but can also be generated on the basis of a new value on the occasion of this initialization. It is for example generated from unique identification data, such as a public data device 30. It can also be generated from parameters or physical phenomena related to the microcircuit at a given instant, which can be random. In all cases, it is stored in memory in a secure manner, to allow the microcircuit to regenerate at any time the same sequence of values (A n ) using the function implemented by section 20 "a.
• initialization INIT can be unique in the life cycle of the microcircuit, made during the design by the manufacturer, or reproduced several times, for example regularly or whenever the counter i reaches an imax value.
• the generator 20 " is solicited one or more times to apply the secret parameter S to the predefined function F, to generate, in one or more times, a number T of elements of the sequence of values (A n ): A 1 , ... A ⁇ . From these first T elements, the protection parameters ⁇ , ... a ⁇ are generated.
• a k A k .
• T C 1 ,... SeC 7 additional secret values T C 1 ,... SeC 7 among the secret parameters S kept in secure memory
• the generator 20 " is again requested one or more times to apply the secret parameter S to the predefined function F, so as to generate, in one or more times, a number T of additional elements of the sequence of values (A n ): A T (M) +1 , ... A 71 .
• the knowledge of the method and the secret values used by the method allows to find at any time the protection parameters generated and used in the life of the device. It is clear that this feature allows simple and efficient debugging as well as improved resistance to fault injection attacks.
• the choice of the method used to generate the sequence of values and the protection parameter (s) is dictated by the intended application.
• 100, 200, 300 and the parameters v, r2, r3 during the steps 102, 202, 302 may be one of those recommended in the second embodiment.
• the parameters v then r1, r2 and r3 can be found in steps 120, 218, 312 without necessarily being kept in memory during the execution of the exponentiation.
• the protection parameter a can also be found to verify that its integrity has been preserved during the exponentiation.
• the method used by the fourth and fifth methods of FIGS. 7 and 8 to generate the protection parameter a during steps 400, 500 and the parameter v during steps 402, 502 may be one of those recommended in FIG. second embodiment.
• the parameter v then r can be found in steps 420, 518 without necessarily being stored in memory during the execution of the scalar multiplication.
• the protection parameter a can also be found to verify that its integrity, and that of the parameters used to generate it, has been retained during the scalar multiplication.
• Additional protection may be added when executing the computation loop of the primitive, in each of the five aforementioned methods.
• the data M, N, d, etc. can be scrambled for not being discovered and an alert can be triggered.
• Other data than M, N and d can be used, from the moment these data are used during the execution of the primitive.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Mathematical Analysis (AREA)
• Mathematical Optimization (AREA)
• Pure & Applied Mathematics (AREA)
• Computing Systems (AREA)
• Computer Security & Cryptography (AREA)
• Computational Mathematics (AREA)
• Mathematical Physics (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• General Engineering & Computer Science (AREA)
• Algebra (AREA)
• Storage Device Security (AREA)
• Complex Calculations (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=39731064

Family Applications (1)

Country Status (8)

Families Citing this family (12)

Family Cites Families (8)

• 2008
  • 2008-01-23 FR FR0800344A patent/FR2926651B1/fr active Active
• 2009
  • 2009-01-23 KR KR1020107018452A patent/KR20100113130A/ko not_active Withdrawn
  • 2009-01-23 JP JP2010543543A patent/JP2011510578A/ja active Pending
  • 2009-01-23 WO PCT/FR2009/000071 patent/WO2009112686A2/fr not_active Ceased
  • 2009-01-23 CA CA2712178A patent/CA2712178A1/fr not_active Abandoned
  • 2009-01-23 EP EP09719837A patent/EP2248009A2/de not_active Withdrawn
  • 2009-01-23 CN CN2009801028938A patent/CN101925875A/zh active Pending
• 2010
  • 2010-07-21 US US12/840,347 patent/US20110274271A1/en not_active Abandoned

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events