EP2780945A1 - Dispositifs et procédés de charge inclinée optique - Google Patents

Dispositifs et procédés de charge inclinée optique

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Publication number
EP2780945A1
EP2780945A1 EP12850478.4A EP12850478A EP2780945A1 EP 2780945 A1 EP2780945 A1 EP 2780945A1 EP 12850478 A EP12850478 A EP 12850478A EP 2780945 A1 EP2780945 A1 EP 2780945A1
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EP
European Patent Office
Prior art keywords
region
base
emitter
providing
collector
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EP12850478.4A
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German (de)
English (en)
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EP2780945A4 (fr
Inventor
Gabriel Walter
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Quantum Electro Opto Systems Sdn Bhd
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Quantum Electro Opto Systems Sdn Bhd
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Publication of EP2780945A1 publication Critical patent/EP2780945A1/fr
Publication of EP2780945A4 publication Critical patent/EP2780945A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/813—Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures

Definitions

  • This invention relates to the field of semiconductor light emitting devices and techniques and, more particularly, to tilted charge light emitting devices and methods.
  • HBTs heterojunction bipolar transistors
  • light-emitting transistors transistor lasers
  • tilted charge light-emitting diodes LETs, TLs, and TCLEDs, all of which are optical tilted charge devices.
  • a tilted charge device gets its name from the energy diagram characteristic in the device's base region, which has, approximately, a descending ramp shape from the emitter interface to the collector (or drain, for a two terminal device) interface. This represents a tilted charge population of carriers that are in dynamic flow - "fast” carriers recombine, and "slow” carriers exit via the collector (or drain).
  • An optical tilted charge device includes an active region with built-in free majority carriers of one polarity. At one input to this active region, a single species of minority carriers of opposite polarity are injected and allowed to diffuse across the active region. This active region has features that enable and enhance the conduction of majority carriers and the radiative recombination of minority carriers. On the output side of the region, minority carriers are then collected, drained, depleted or recombined by a separate and faster mechanism. Electrical contacts are coupled to this full-featured region.
  • Tilted charge light-emitting devices for example of the types disclosed in documents listed above (for example, in the form of light-emitting transistors and tilted charge light-emitting transistors and tilted charge light-emitting diodes) can produce spontaneous light emission at relatively high speed and bandwidths. For some applications, however, it would be desired to have tilted charge spontaneous light emitting devices and techniques that can operate at much higher speeds and bandwidths, and the achievement of such devices and techniques are among the objectives of one of the aspects of the present invention.
  • QW- HBLET QW-heterojunction bipolar light emitting transistor
  • the relatively deep QW assists captured carriers to spread laterally and recombine away from the optical cavity.
  • the carriers can also rethermalize and carriers that rethermalize towards the emitter (back diffusion) are mostly lost in to non-radiative recombination.
  • an asymmetrical base region was set forth, having a relatively wider bandgap base sub- region on the emitter side the QW as compared to a relatively narrow bandgap sub- region on the collector side.
  • one or more shallow quantum wells were used for reasons that include limiting diffusion of captured carriers and increasing speed.
  • Applicant's research has indicated that the use of heavily doped high composition alloy (e.g. ternary or quaternary material) in the base region of an optical tilted charge device (OTCD), can result in significantly higher non-radiative recombination ( ⁇ -rad ⁇ 30% to 90% of base recombination).
  • Some of this research has been focused on the use of a relatively shallow InGaAs quantum well ( ⁇ , the quantum well depth energy, is a small multiple of kT, ⁇ -kT ) with emission photon energies that can be coupled to InP/lnGaAs based photodetectors.
  • optical tilted charge devices share few common design traits with the high speed HBT transistor (an electrical tilted charge device).
  • An optical tilted charge device has a quantum size region (typically, one or more quantum wells) in its base region.
  • a quantum well in the base of a transistor does not merely introduce another element or defect to assist in recombination, but also a structure which is capable of storing charge, lateral transport, and re-thermalizing of captured carriers. Furthermore, with significantly lower electrical gain (higher base current ratios), problems associated with base sheet resistance (heating, emitter crowding) and base current densities (reliability) is amplified and the importance of base transit time, a big issue in design of HBT's, is dwarfed by concerns of lateral resistance and emitter crowding at low emitter current densities.
  • optical extraction, beam shape and optical power output can be as important as the electrical gain and electrical bandwidth of the device.
  • the high speed tilted optical charge device shares few common design traits with charge storage light emitters (i.e., diode lasers or light emitting diodes).
  • charge storage light emitters i.e., diode lasers or light emitting diodes.
  • the design rules of an optical charge storage device necessitate methods of maximizing confinement or storage of carriers (to improve the probability of stimulated emission process where captured carriers "wait" to be stimulated by a photon field or recombine by spontaneous emission), whereas the design rules of an optical tilted charge device necessitate the minimization of stored carriers.
  • design rules for light extraction used in charge storage devices do not simply apply to tilted charge devices due to the physical design restrictions imposed on the tilted charge device (different geometry) and high speed application (e.g.
  • an aspect of the invention involves reducing non-radiative recombination associated with base surface recombination.
  • Another aspect of the invention involves reduction of base charge capacitance associated with the lateral transport and unintentional confinement of electrons in the quantum well.
  • a quantum well (QW) in a heterojunction bipolar transistor (HBT) in conjunction with a thin base layer thickness (the "base 1 " region) between the QW and the base surface introduces the problem of carriers tunneling from the quantum well into the surface states where they recombine non-radiatively.
  • a thin base layer thickness the "base 1 " region” between the QW and the base surface
  • a layer thickness of less than about 300 Angstroms introduces the problem of carriers tunneling from the quantum well into the surface states where they recombine non-radiatively.
  • Use of an asymmetric base region as a technique for reducing thermalization of captured electrons in QW towards the surface has previously been disclosed (see U.S. Patent Application Publication No. US2010/0202484). This helps in reducing non-radiative recombination and since electron re-thermalization is preferred toward the collector, it also assists in reducing lateral transport of electrons.
  • the larger bangap region of the asymmetric base region also acts to reduce
  • a tunneling barrier structure comprising, for example, a low doped (1 E-16 cm “3 to 5E-1 7 cm “3 ) or unintentionally doped n-type layer structure of thickness preferably between about 15 to 50 nm, can be used to increase the spatial distance from the quantum well to the surface, thereby reducing tunneling of captured carriers in the quantum well to the surface states without having to physically increase the p-type base region between the quantum well and emitter region.
  • the tunnel barrier structure material should preferably have an energy gap greater than the fundamental states of the quantum well, and should be selectively removable by an etching process that will not affect the base 1 region.
  • the tunnel barrier can, for example, be made of relatively higher Al % (>35%), AIGaAs or lattice matched or be a strained InAIGaP alloy layer.
  • An asymmetric base design, with increasingly higher energy barrier, can also be employed in conjunction with the above-described ledge to increase the tunneling barrier height, to generate preferential conditions of carrier re-thermalization towards the collector, and to increase the barrier height, which also reduces tunneling.
  • a method for producing optical signals with improved efficiency, including the following steps: providing a layered semiconductor structure that includes a substrate, a semiconductor collector region of a first conductivity type, a semiconductor base region of a second conductivity type disposed on said collector region, and a semiconductor emitter region of said first semiconductor type disposed as a mesa over a portion of a surface of said base region; providing, in said base region, at least one region exhibiting quantum size effects; providing collector, base, and emitter electrodes, respectively coupled with said collector, base and emitter regions; providing a tunnel barrier layer over at least the exposed portion of said surface of said base region; and applying signals with respect to said collector, base, and emitter electrodes to produce optical signals from said base region.
  • the step of providing said electrodes includes providing at least a portion of said base electrode as being disposed on said surface of said base region and spaced from said emitter mesa, and said step of providing said tunnel barrier layer comprises providing said tunnel barrier layer on said surface of said base region between said mesa and said base electrode.
  • said step of providing said at least one region exhibiting quantum size effects comprises providing a discontinuous or non-planar quantum size region; that is, quantum dots and/or quantum wires (discontinuous), or a corrugated quantum well (non-planar).
  • said step of providing said base region comprises providing a base region that includes a first base sub-region on the emitter side of said quantum size region, and a second base sub-region on the collector said of said quantum size region, and said first and second base sub-regions are provided with asymmetrical band structures with respect to each other.
  • a method for producing a tilted-charge light-emitting device, including the following steps: forming a layered semiconductor structure that includes a substrate, a semiconductor collector region of a first conductivity type, a semiconductor sub-base region of a second conductivity type, a quantum size region, and a further semiconductor sub- base region of said second conductivity type; depositing a tunnel barrier layer on said further sub-base region; forming a semiconductor emitter mesa of said first conductivity type on a portion of the surface of said barrier layer; and providing collector, base, and emitter electrodes respectively coupled with said collector, base, and emitter regions.
  • said barrier layer is deposited over a non-peripheral portion of a surface of said further sub-base region, and said step of forming said base electrode comprises forming said base electrode on a peripheral portion of said further sub-base region, spaced from said emitter mesa.
  • said step of forming said base sub-region and said further base sub-region comprises forming said base sub-region and further base sub-region as having asymmetrical band structures with respect to each other. This can be implemented by forming said further base sub-region with higher bandgap semiconductor material than the semiconductor material of said sub-base region.
  • said further base sub-region is formed with a thickness of less than about 30 nm.
  • a tilted- charge light-emitting semiconductor device comprising: a layered semiconductor structure that includes a substrate, a semiconductor collector region of a first conductivity type, a semiconductor base region of a second conductivity type disposed on said collector region, and a semiconductor emitter region of said first semiconductor type disposed as a mesa over a portion of a surface of said base region; said base region including at least one region exhibiting quantum size effects; collector, base, and emitter electrodes, respectively coupled with said collector, base and emitter regions; and a tunnel barrier layer disposed over at least the exposed portion of said surface of said base region; whereby, signals applied with respect to said collector, base, and emitter electrodes can produce optical signals from said base region.
  • At least a portion of said base electrode is disposed on said surface of said base region and spaced from said emitter mesa, and said tunnel barrier layer is disposed on said surface of said base region between said mesa and said base electrode.
  • said at least one region exhibiting quantum size effects comprises a discontinuous or non-planar quantum size region.
  • a method for producing optical signals with improved efficiency, including the following steps: providing a layered semiconductor structure that includes a substrate, a
  • said step of providing said electrodes includes providing at least a portion of said base/drain electrode as being disposed on said surface of said base region and spaced from said emitter mesa, and wherein said step of providing said tunnel barrier layer comprises providing said tunnel barrier layer on said surface of said base region between said mesa and said base/drain electrode.
  • the design of a practical optical tilted charge device includes several complex considerations including achievement of high internal quantum efficiency,
  • an optical tilted charge device with a deep quantum well with ⁇ at least about 0.25 eV » kT
  • the optical tilted charge device with these features is still capable of incorporating etch stop layers that selectively stop etching at one type of semiconductor material, to assist in the definition of the emitter mesa, base mesa and collector mesa which benefits manufacturability.
  • the base region can still be doped with carbon (p-type, NPN structure) or silicon (n-type, PNP).
  • Compatibility is maintained, since the emission photon energies of the optical tilted charge device can still be coupled to existing InP/lnGaAs based photodetectors.
  • a further advantage is that the disclosed GaAs based optical tilted charge device hereof is compatible with the use of silicon-based substrates and lenses.
  • a method for making an optical tilted-charge device that is substantially matched to GaAs lattice constant, including the following steps: providing a layered semiconductor structure that includes: a GaAs substrate; a semiconductor collector region; a semiconductor base region that includes a doped GaAs second base sub-region, an InGaAsN quantum size region, and a doped GaAs first base sub-region; and a semiconductor emitter region; and providing collector, base, and emitter electrodes respectively coupled with said collector region, said base region, and said emitter region.
  • the step of providing said collector and emitter regions comprises providing said regions as substantially GaAs
  • the step of providing said second and first base sub-regions comprises providing said second and first base sub- regions as being heavily doped p-type (where, as used herein, heavily doped means at least about 1 0 18 cm "3 for p-type and 10 17 cm “3 for n-type).
  • the step of providing said InGaAsN quantum size region comprises providing an InGaAsN quantum well between GaAs barrier layers.
  • the step of providing said InGaAsN quantum size region can comprise providing a plurality of InGaAsN quantum wells, each between GaAs barrier layers. Also in this
  • the method includes growing said layered semiconductor structure with intervening InAIGaP alloy etch stop layers for defining base and emitter mesas using an etchant that selectively removes arsenide-based materials.
  • the InAIGaP alloy for this etch stop application also includes the use of InGaP or InAIAs etch stop layers.
  • the layered semiconductor structure is deposited on a GaAs-on-Si substrate, and a Si lens is formed from said substrate.
  • a method for making a two- terminal optical tilted-charge device that is substantially matched to GaAs lattice constant, including the following steps: providing a layered semiconductor structure that includes: a GaAs substrate; a semiconductor drain region; a semiconductor base region that includes a doped GaAs second base sub-region, an InGaAsN quantum size region, and a doped GaAs first base sub-region; and a semiconductor emitter region; and providing a base/collector electrode coupled with said collector and base regions, and an emitter electrode coupled with said emitter region. Electrical signals, applied with respect to said base/drain and emitter electrodes, produces light emission from said base region.
  • an optical tilted-charge device that is substantially matched to GaAs lattice constant, comprising: a layered semiconductor structure that includes: a GaAs substrate; a semiconductor collector region; a semiconductor base region that includes a heavily doped GaAs second base sub-region, an InGaAsN quantum size region, and a heavily doped GaAs first base sub-region; and a semiconductor emitter region; said collector and emitter regions being of opposite conductivity type to the conductivity type of said base sub- regions; and collector, base, and emitter electrodes respectively coupled with said collector region, said base region, and said emitter region; whereby application of electrical signals with respect to said collector, base, and emitter electrodes will produce light emission from said base region.
  • the InGaAsN quantum size region in said base region comprises a quantum well having a depth of at least about 0.25 eV.
  • the InGaAsN quantum size region comprises an InGaAsN quantum well between GaAs barrier layers.
  • the InGaAsN quantum size region comprises ln x Gai- x AsN with x at least about 0.3.
  • the GaAs substrate is disposed on silicon, and said silicon is in the form of a lens.
  • Figure 1 is a cross-sectional view of an optical tilted charge device, in the form of a light-emitting transistor, in accordance with an embodiment of the invention and which can be used in practicing an embodiment of the method of the invention.
  • Figure 2 is a table showing the epilayer structure of an example of the Figure 1 device wherein the quantum well is within tunneling distance to the surface of the base.
  • a tunnel barrier of the same material as the emitter is used.
  • An asymmetric base is used to favor re-thermalization towards the collector and increase the barrier height.
  • the tilted charge device epilayers are designed to be compatible with HBT foundry processes.
  • Figure 3 is a table showing the processed device DC characteristics for devices fabricated using the structure of Figures 1 and 2.
  • Figure 4 is a graph of light output as a function of base current for the devices of Figures 1 and 2.
  • the distance between emitter mesa edge and base metal edge was varied from 1 .5 ⁇ to 7 ⁇ while keeping all other dimensions the same.
  • Figure 5 is a graph which plots the capacitance C D versus the distance d.
  • AC analysis indicates that as the distance d is varied from 1 .5 urn to 7 urn, the capacitance associated with the electron dynamics (i.e. charge storage capacitance, diffusion capacitance), increases. As only the lateral dimensions (d) were altered, this indicates that the capacitance area has increased due to the lateral travel of electrons via the QW, thus populating a larger area of the quantum well.
  • the capacitance associated with the electron dynamics i.e. charge storage capacitance, diffusion capacitance
  • Figure 6 is a cross-sectional view of another optical tilted charge device similar to the device of Figure 1 (with like reference numerals representing similar elements), but with the device base region having a discontinuous quantum structure in the form of quantum dots, in the base region.
  • Figure 7 is a table showing the epilayer structure of a device in accordance with another embodiment of the invention. An asymmetric base and discontinuous quantum structure are incorporated into the design. Re-thermalization toward the collector is favored.
  • Figure 8 is a table showing epilayer structure of a device in accordance with another embodiment of the invention, wherein a corrugated quantum well is employed.
  • Figure 9 is a table showing the epilayer structure of a device in accordance with another embodiment of the invention, wherein a narrow quantum well is used in combination with a discontinuous quantum structure.
  • Figure 10 is a cross-sectional view of an optical tilted charge device, in the form of a light-emitting transistor, in accordance with another embodiment of the invention and which can be used in practicing another embodiment of the method of the invention.
  • Figure 1 1 is a table showing the epilayer structure of an example of the Figure 10 embodiment of the invention.
  • Figure 12 is a table showing the epilayer structure of a device in accordance with another embodiment of the invention.
  • Figure 13 is a cross-sectional view of another optical tilted charge device, in the form of a two-terminal tilted charge light-emitting diode, in accordance with a further embodiment of the invention and which can be used in practicing a further embodiment of the method of the invention.
  • FIG. 1 there is shown a cross-sectional view of an optical tilted charge device, in the form of a light-emitting transistor, in accordance with an embodiment of the invention and which can be used in practicing an embodiment of the method of the invention.
  • a subcollector region 125 is disposed on an undoped substrate 1 10.
  • a mesa on subcollector 125 includes a base region 140 disposed between a collector region 130 and an emitter region 160 formed on a further mesa.
  • the base region includes one or more quantum wells 145 between an upper base region (base 1 ) and a lower base region (base 2).
  • a collector electrode 127 contracts a surface of subcollector region 125
  • a base electrode 147 contacts a surface of base region 140
  • an emitter electrode 167 contacts a surface of emitter region 160.
  • a tunnel barrier layer 150 is disposed over the top surface of the base region 140, between the base region and emitter region 160, covering, inter alia, the exposed portion of the surface of the base region.
  • the table of Figure 2 shows an example of a representative epilayer structure for the embodiment of Figure 1 .
  • the epilayer structure can be made using existing MOCVD (metalorganic vapor deposition) and/or MBE (molecular beam epitaxy) deposition techniques, and the devices formed using existing photolithography techniques.)
  • MOCVD metalorganic vapor deposition
  • MBE molecular beam epitaxy
  • the upper quantum well (layer 9) is within tunneling distance (24 urn) to the surface of base 140 (i.e., the surface of base 1 - layer 1 2).
  • a tunneling barrier 150 (layer 13) of the same material as the emitter 160 (layer 14) us used; namely ln 0. 9 Ga 0.5 iAs.
  • An asymmetric base is used to favor re-thermalization toward the collector and increase the barrier height.
  • the tunnel barrier structure increases the distance (and reduces tunneling probability) between the carriers in the quantum well to the surface states. Without the tunnel barrier, as indicated, the tunneling distance between the quantum well and the surface state is 24 nm. With the tunnel barrier, this distance is increased to 78 nm ( ⁇ 3 times). Tunneling probability may also be reduced by increasing the thicknesses of layer 1 1 and 1 2 (base 1 ) of the epi- structure.
  • the use of the tunnel barrier allows design that does not require a thick base 1 region (e.g. for base transit time reasons or material reasons).
  • the third column includes, for some layers, the designation "ELDL", which stands for the optional use of engineered long diffusion length material for these layers.
  • ELDL the optional use of engineered long diffusion length material for these layers.
  • U.S. Patent Application Publication US 2012/006815 which describes the use of such material. It will be understood, however, that the present invention does not require the use of this optional material.
  • the third column of the tables hereof also lists a
  • the photon (wavy) arrows indicate that usable light can be extracted either from the top or from the bottom side.
  • base contact Ti-Pt-Au
  • emitter contact Au-Ge
  • collector contact Au-Ge
  • the device is operated with the base-emitter junction in forward bias (e.g. V B E > 1 .2 volts) and the base-collector junction in high impedance mode (not necessary reversed bias - e.g. -2.5 volts ⁇ V B c ⁇ 0.5 volts).
  • Carrier movement is depicted by solid arrows.
  • the total effective tunnel barrier thickness, where emitter is present is accordingly greater.
  • the use of dissimilar materials for the emitter and tunnel barrier, for example AIGaAs emitter and InAIGaP tunnel barrier can allow the layers to be separated during processing.
  • a thin 21 nm doped AIGaAs graded layering (layers 1 1 and 12, with Al content of 0.5% to 5%) are used to increase the barrier height and to favor re-thermalization toward the collector.
  • a 3 nm undoped GaAs buffer layer (layer 10) is added to reduce the contamination of dopants into the quantum well.
  • the tilted charge device epilayers are designed to be compatible with HBT foundry processes.
  • the processed device DC characteristics are shown in the table of Figure 3. Fabricated devices were lapped to 150 ⁇ , and measured.
  • recombination at the surface also assists in reducing the formation of heat spots at the surface (which is an amplified issue in a low current gain transistor such as a light emitting transistor), that could lead to base-emitter leakage and reliability issues.
  • an embodiment hereof utilizes a discontinuous quantum structure (DQS) as the quantum size region in the device's base region.
  • DQS discontinuous quantum structure
  • the DQS such as the quantum dots or quantum wires, provides energy gap discontinuities along the lateral axis.
  • FIG. 6 illustrates a device similar to the device of Figure 1 (with like reference numerals representing similar elements), but with the device base region (designated 140') having a discontinuous quantum structure, in the form of quantum dots 645, in the base region.
  • the DQS structure may be incorporated during growth of epitaxial layers (see the table of Figure 7), or by patterning of quantum structures followed by a re- growth method.
  • thin n-type InGaAs layers (less than 100 nm) were used in order to enable use of non-alloy contact which is optically smoother compared to alloyed contacts such as AuGe.
  • the resulting smoother contact layer will improve light extraction from the bottom of the substrate by reflecting photons downward.
  • the exposed emitter mesa width (W) may be reduced or eliminated (e.g. by self-aligned methods) so that the entire emitter mesa width is covered by the reflecting non-alloy contact, in order to increase bottom light extraction.
  • the thickness of the InGaAs layers are preferably thin enough to reduce photon self-absorption, but thick enough to enable the use of non-alloy contacts.
  • an asymmetric DQS is incorporated into the design to favor re-thermalization toward the collector.
  • other DQSs such as quantum wires, may also be used instead of quantum dots.
  • Relatively thin tellerium doped InGaAs sub-emitter layers are used to enable the use of Ti-Pt-Au contacts for the emitter.
  • Ti-Pt-Au provides better reflectivity as compared to Au-Ge alloy contacts, and will offset the photon absorption loss due to the use of low bandgap InGaAs sub-emitter layers.
  • the discontinuous quantum structure is used to prevent the lateral transport of electrons towards the base contact.
  • the edge recombination process is this Figure is exaggerated to indicate that the tilted charge device is an edge recombination device. It will be evident that by shrinking the emitter mesa dimensions it is possible to eventually obtain a "uniform" recombination distribution under the emitter mesa. Photon arrows indicate that usable light can be extracted either from the top or from the bottom side.
  • Base contact Ti-Pt-Au
  • emitter contact Ti-Pt-Au
  • collector contact Au-Ge
  • the device is operated with the base-emitter junction in forward bias and the base- collector junction in high impedance mode (not necessary reversed bias).
  • a partial DBR or full DBR cavity may also be incorporated into this structure.
  • embodiment, and others hereof can also be operated as a laser by providing a suitable resonant optical cavity.
  • lateral conduction of minority carrier is reduced by the use of single or multiple highly strained corrugated (non-planar) quantum wells (C-QW) (for example, InGaAs QW in a InGaP/GaAs LET, with indium composition of more than about 20%), where the quantum well width is defined as the distance between the two barriers confining the fundamental recombination state of the quantum well.
  • C-QW non-planar quantum wells
  • Indium composition and corrugation of quantum well can be verified using methods such as SIMS (secondary ion mass spectrometry) analysis, AFM (atomic force microscopy), FIB (focused electron beam), or high resolution TEM (transmission electron microscope).
  • the highly strained surfaces result in growth of non-planar (corrugated) QW surfaces.
  • QW surfaces Reference can be made for example, to T. Chung, G. Walter, and N. Holonyak, Jr., "Coupled Strained Layer InGaAs Quantum Well Improvement of an InAs Quantum Dot AIGaAs-GaAs-lnGaAs- InAs Heterostructure Laser," Appl. Phys. Lett. 79, 4500-4502 (2001 ); G. Walter, T. Chung, and N.
  • corrugated QWs can be enhanced with the use of off axis substrates or pre-patterned substrates (for example, selective crystal planes or by photolithography/etching processes).
  • a corrugated or non-planar surface provides optical and electrical wave function perturbations which distorts carrier mobility.
  • the epilayer structure set forth in the table of Figure 8 is for an embodiment of a tilted charge device wherein a corrugated quantum well (C-QW) is embedded with a main emission peak designed around 1020 nm.
  • a 1020 nm emission peak light emitter may be used with high-OH (UV/VIS) fibers.
  • An asymmetric C-QW is used in this embodiment to favor re-thermalization toward the collector and to increase tunneling distance. If needed, aluminum composition in layer 6, 1 0 and/or 1 1 may be increased to reduce the emission wavelength from 1020 nm to, say, 1000 nm without having to reduce indium composition.
  • the epilayer structure of which is shown in the table of Figure 9 a narrow quantum well (planar QW or C-QW) is used in combination with a DQS to provide improved carrier capture ability and to assist in material growth of the DQS.
  • the tilted charge device includes a thin planar quantum well (QW) coupled via a tunneling barrier to a 5 mono layer (ML) DQS with a main emission peak designed around (but not necessarily) 1020 nm.
  • the quantum well may be designed to have a peak emission wavelength of 1020 nm (-same energy) or 980 nm (-higher energy).
  • a 1020 nm emission peak light emitter may be used with high-OH fibers.
  • An asymmetric DQS is used in this design to favor re- thermalization toward the collector and to increase tunneling distance.
  • the features of the invention are employed in a two terminal tilted-charge light-emitting diode, of the general type disclosed in U.S.
  • Patent Application Publication No. US2010/0202483 or U.S. Patent Application Publication No. US2012/0068151 the structure of the Figure 1 or 6 embodiments is varied, with the region beneath the base region being designated a drain region, and a peripheral base/drain electrode is coupled with the base region and the drain region.
  • the base region including at least one quantum size region that is preferably discontinuous or corrugated, is provided as in the prior
  • a tunnel barrier layer is
  • Figure 10 shows a device in accordance with another embodiment of the invention, and which can be used in practicing another embodiment of the method of the invention.
  • the semiconductor layering shown in Figure 10, from the bottom up includes: a GaAs substrate 1 1 10; a GaAs buffer region 1 120; a sub-collector region 1 130; a collector region 1 140; a base region 1 1 60 that includes a base sub-region 1 162 called “base-2", a quantum size region 1 150 (one or more quantum wells or other suitable quantum size regions such as quantum dots or quantum wires), a base sub-region 1 1 67 called “base-1 ", an emitter region 1 170, and a sub-emitter region 1 180.
  • a GaAs substrate 1 1 10 includes a GaAs buffer region 1 120; a sub-collector region 1 130; a collector region 1 140; a base region 1 1 60 that includes a base sub-region 1 162 called “base-2", a quantum size region 1 150 (one or more quantum wells or other suitable quantum size
  • an InGaAsN quantum size region is employed in the base region.
  • the collector, base, and emitter electrodes are shown respectively as metal collector contact 1 135 (which contacts the subcollector region), metal base contact 1 165 (which contacts the base-1 region), and metal emitter contact 1 185 (which contacts the sub-emitter region).
  • a collimator or focusing lens 1 105 can be molded to or affixed to the GaAs substrate 1 1 1 0.
  • the collimator or lens 1 105 can be advantageously formed of silicon.
  • the lens can be formed by etching the silicon.
  • a bottom light emitter is shown, the device can also be configured as a top emitter.
  • the table of Figure 1 1 shows the more detailed semiconductor epilayers of an example of the Figure 10 embodiment.
  • the epilayer structure can be made using existing MOCVD (metalorganic vapor deposition) and/or MBE (molecular beam epitaxy) deposition techniques, and the devices formed using existing MOCVD (metalorganic vapor deposition) and/or MBE (molecular beam epitaxy) deposition techniques, and the devices formed using existing MOCVD (metalorganic vapor deposition) and/or MBE (molecular beam epitaxy) deposition techniques, and the devices formed using existing
  • MOCVD metalorganic vapor deposition
  • MBE molecular beam epitaxy
  • the base-2 region includes a p-type GaAs layer (layer 6), followed by a lower doped p-type GaAs material (layer 7) to complete the base-2 region.
  • the dopant is reduced closer to the quantum well to reduce the diffusion of dopants into the quantum well region.
  • the dopant for the p-type base region is preferably carbon, which has a relatively abrupt diffusion tail compared to most other p-type dopants such as zinc.
  • a quantum well structure including an unintentionally doped GaAs layer (layer 8) is grown to form the first barrier layer, followed by a thin (-120 A) lower bandgap InGaAsN layer, which is substantially lattice matched to GaAs (layer 9), and then completed with another thin GaAs layer as the second barrier layer (layer 10).
  • a multiple quantum well structure may alternatively be implemented by using repetitious layers of InGaAsN and GaAs barrier layers, as shown in the table of Figure 12.
  • the active base region of the device is then completed with the growth of the base-1 structure, including lower doped p-type GaAs layer (layer 1 1 ) and a higher doped GaAs contact layer (layer 12).
  • Layer 14 is shown in the table as having a possibility of aluminum content, such as for index step or confinement using lateral oxidation.
  • InGaAsN semiconductor material advantageously used for the quantum well hereof, is a quaternary material which uses smaller nitrogen atoms to compensate for the strain induced by the larger indium atoms, allowing the material to remain substantially matched to GaAs lattice constant. This allows higher incorporation of indium to lower the energy gap of the InGaAsN layer, resulting in a deeper quantum well, without having to increase the energy gap of the barrier layers which would require resorting to ternary composition.
  • InGaAsN material for the quantum well also allows for the design of devices with emission peak longer than 1 100 nm, which has relatively high transmission through silicon. This allows the optical tilted charge devices to be advantageously coupled to high index silicon lenses (as in Figure 10). Since the entire OTCD structure is substantially lattice matched to GaAs lattice constants, and the emission wavelength can be tailored to enable the use of silicon lenses, the disclosed devices can be directly grown on GaAs-on-Si substrates, and the lens etched from the Si. Also, for GaAs substrates, an alternative is to etch a lens in the GaAs.
  • low doped, and substantially matched to GaAs lattice constant, InAIGaP alloy e.g. ln 0 . 4 9Ga 0 .5i P
  • etch stop layers are placed in Layer 1 , 4 and 13, which also define the boundaries for the base contact layer (layer 13), the collector contact layer (layer 3) and the boundary (layer 1 ) between the doped and undoped buffers.
  • Layer 1 can be used to assist in the GaAs substrate removal or device isolation by allowing all conducting material to be removed and therefore electrically decoupling one device from another adjacent device.
  • These phosphide based materials e.g.
  • InGaP or InAIGaP are stable relative to etchant used to remove the arsenide based materials such as GaAs and InGaAs.
  • the phosphide based materials can be removed using etchant that is stable against arsenide based material. Accordingly, the phosphide based materials can be removed without affecting the arsenide materials and vice versa.
  • a partial DBR or full DBR cavity may also be incorporated into this structure. This embodiment, and others hereof, can also be operated as a laser by providing a suitable resonant optical cavity.
  • the features of the invention are employed in a two terminal tilted-charge light-emitting diode, of the general type disclosed in U.S. Patent Application Publication No. US2010/0202483 or U.S. Patent Application Publication No. US2012/0068151 .
  • the structure of the Figure 10 embodiment is varied, with the region beneath the base region being designated a drain region, and a peripheral base/drain electrode being coupled with the base region and the drain region.
  • FIG. 1 3 An example is shown in Figure 1 3, in which lens 1 105, substrate 1 1 10, buffer region 1 120, base-1 region 1 162, quantum size region 1 150, base-2 region 1 167, emitter region 1 170, sub-emitter region 1 180, and emitter contact 1 1 85 are similar to elements of like reference numerals in Figure 10.
  • the Figure 13 device has subdrain region 1430 and drain region 1440.
  • the device of this embodiment has a base/drain electrode 1465.
  • application of electrical signals to said base/drain and emitter electrodes produces light emission from the base region.
  • the tilted-charge light-emitting diode of this embodiment has the same advantages in fabrication and operation as the three terminal optical tilted charge device of the Figure 10 embodiment.

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  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un procédé de production de signaux optiques avec une efficacité améliorée, dont les étapes consistent : à produire une structure semi-conductrice stratifiée qui comprend un substrat, une zone de collecteur semi-conductrice d'un premier type de conductivité, une zone de base semi-conductrice d'un second type de conductivité disposée sur la zone de collecteur, et une zone d'émetteur semi-conductrice du premier type semi-conducteur disposée comme une mesa sur une partie d'une surface de la zone de base ; à produire, dans la zone de base, au moins une zone présentant des effets de taille quantique ; à produire des électrodes de collecteur, de base, et d'émetteur, respectivement couplées aux zones de collecteur, de base et d'émetteur ; à produire une couche de barrière à effet tunnel sur au moins la partie exposée de la surface de la zone de base ; et à appliquer des signaux par rapport aux électrodes de collecteur, de base et d'émetteur pour produire des signaux optiques à partir de la zone de base. L'invention concerne aussi un dispositif de charge inclinée optique avec un puits quantique d'InGaAsN.
EP12850478.4A 2011-11-14 2012-11-13 Dispositifs et procédés de charge inclinée optique Withdrawn EP2780945A4 (fr)

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US6593589B1 (en) * 1998-01-30 2003-07-15 The University Of New Mexico Semiconductor nitride structures
US6756325B2 (en) * 2002-05-07 2004-06-29 Agilent Technologies, Inc. Method for producing a long wavelength indium gallium arsenide nitride(InGaAsN) active region
US7244997B2 (en) * 2003-07-08 2007-07-17 President And Fellows Of Harvard College Magneto-luminescent transducer
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US8509274B2 (en) * 2009-01-08 2013-08-13 Quantum Electro Opto Systems Sdn. Bhd. Light emitting and lasing semiconductor methods and devices
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