Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
  • H10F19/90—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers
  • H10F19/902—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers for series or parallel connection of photovoltaic cells
  • H10F19/906—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers for series or parallel connection of photovoltaic cells characterised by the materials of the structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F10/00—Individual photovoltaic cells, e.g. solar cells
  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
  • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
  • H10F10/167—Photovoltaic cells having only PN heterojunction potential barriers comprising Group I-III-VI materials, e.g. CdS/CuInSe2 [CIS] heterojunction photovoltaic cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
  • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
  • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
  • H10F19/33—Patterning processes to connect the photovoltaic cells, e.g. laser cutting of conductive or active layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
  • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
  • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
  • H10F19/35—Structures for the connecting of adjacent photovoltaic cells, e.g. interconnections or insulating spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/128—Annealing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/137—Batch treatment of the devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/10—Semiconductor bodies
  • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
  • H10F77/169—Thin semiconductor films on metallic or insulating substrates
  • H10F77/1694—Thin semiconductor films on metallic or insulating substrates the films including Group I-III-VI materials, e.g. CIS or CIGS
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/541—CuInSe2 material PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the invention relates to the field of photovoltaic solar energy and more particularly to thin-film photovoltaic modules.
• a “thin layer” will be a layer having a thickness of less than 5 ⁇ m.
• a photovoltaic module comprises several solar cells placed in series. Indeed, the voltage generated at the terminals of a single solar cell, less than 1 volt, is generally too low for many devices. Serialization of many cells is therefore necessary. Thus, the voltage delivered by a photovoltaic module is of the order of 100 volts, for a hundred cells connected in series.
• the monolithic interconnection process for thin-film solar cells requires three etching steps, conventionally known as P1, P2, P3.
• the first step (P1) provides electrical isolation of two adjacent cells at the back-side electrode of the solar cells.
• the second step (P2) makes it possible to connect the electrode on the front face of a given cell to the electrode on the rear face of the adjacent cell.
• the third step (P3) consists of electrically isolating two adjacent cells at the electrode on the front face.
• etching techniques have the advantage that they can be used for a wide variety of materials deposited in thin layers, for example CdTe, a-Si, CZTS (of general formula Cu 2 ZnSn (S, Se) 4 ) or CIGS ( of general formula Cu (In, Ga) (Se, S) 2 ).
• the mechanical etching leads to the damage of the materials due to the presence of mechanical stresses on the layers, to the formation of debris on the surface of the layers near the etching line which can lead to short-term problems. circuit, as well as the wear of the etching tips.
• the quality of the mechanical etching is very sensitive to many parameters such as the morphology or the properties of the thin layers, as well as to the operating parameters of the etching tips.
• laser ablation is not easy to implement. Indeed, it can be seen that the removed material can melt and partially reseal the groove made by laser ablation. Thus, this technique does not provide a clean surface necessary to achieve a good quality electrical contact. It is also possible to use chemical etching methods. However, these methods are more complicated and more expensive to implement than conventional methods of mechanical etching or laser ablation.
• FIGS. 1a to 1f All these figures are sectional views and represent different stages of implementation of this method.
• Figure 1a shows a substrate 1 which can be made of various materials, including glass, or plastic or metal (eg steel, aluminum, or titanium), flexible or rigid.
• a substrate 1 which can be made of various materials, including glass, or plastic or metal (eg steel, aluminum, or titanium), flexible or rigid.
• this substrate is made of soda-lime glass whose thickness is a few millimeters and typically between 1 and 3 mm.
• a layer of molybdenum 11 is deposited, the thickness of which is generally between 100 nm and 2 ⁇ m, and preferably of the order of 1 ⁇ m.
• This layer of molybdenum will be used to constitute the electrode on the back of the various cells forming the photovoltaic module.
• FIG. 1a shows that an etching step is performed after the deposition of the Mo layer. As indicated above, this etching is generally carried out, either mechanically or by laser ablation. It leads to the formation of a groove 110, devoid of molybdenum.
• This groove 110 makes it possible to define the rear face electrodes 11a and 11b of the adjacent cells 2 and 3 illustrated in FIG. 1f.
• This etching step corresponds to the step P1 mentioned above.
• the width of the groove 110 is generally between 10 ⁇ m and 100 ⁇ m, and it is preferably of the order of 50 ⁇ m.
• FIG. 1b illustrates another step of the process in which a photovoltaic layer is produced and, for example, a crystallized CIGS layer.
• This layer has a function of light absorber.
• This step consists firstly in providing, on the rear face electrode 11, metal precursors of Cu, In, Ga, and elements of the Se and / or S type, used for the growth of the CIGS layer, semiconductor material of type p.
• These may be vacuum processes, such as evaporation or sputtering, or processes carried out at atmospheric pressure, such as electrodeposition, screen printing, doctor-blading, inkjet slit-coating.
• precursors of Cu, In and Ga can be deposited by cathodic sputtering.
• a layer of Se and / or S can then be deposited on the stack obtained by a vacuum method or a method implemented at atmospheric pressure.
• the chalcogen S or Se can be provided in the form of an elemental gas, in the form of gas (H 2 S or H 2 Se) or in the form of a layer of S or Evaporated, deposited on the surface of the layer metal precursors.
• H 2 S and H 2 Se gases are highly toxic, which greatly complicates their use on an industrial scale.
• the thickness of this layer of metal precursors is generally between 300 nm and 1 ⁇ m.
• the conversion of the constituents into a layer 12 of crystallized CIGS is carried out by high temperature annealing, referred to as selenization / sulfurization annealing, using a ramp for increasing the temperature between 1 ° C./s and 10 ° C./s.
• the temperature is generally between 400 and 600 ° C. PT / IB2013 / 050179
• the layer of constituents may be covered with a cover, preferably made of graphite.
• This cover makes it possible to ensure a partial pressure of Se and / or S that is greater during annealing, which leads to increasing the diffusion of Se and / or S in the metal precursors.
• FIG. 1c shows another step of implementing the method, in which an n-type semiconductor layer 13 is deposited on the CIGS layer, in order to form the pn junction.
• This layer may be deposited by chemical bath, by sputtering or by evaporation.
• It may for example be composed of CdS and deposited by chemical bath, the layer 13 having a thickness of a few tens of nm.
• ZnS Zero-semiconductor
• ZnOS Zero-semiconductor
• Other materials may be used such as ZnS or ZnOS, for a thickness for example between 5 nm and 30 nm.
• Figure 1c also illustrates another process step which is optional. This step consists of depositing a layer 14 of intrinsic ZnO, the function of which will be explained later.
• This layer 14 is highly transparent in the solar spectrum and highly resistive. It is generally deposited by sputtering and has a thickness of a few tens of nm.
• the layer 13 prevents reactions between the ZnO and the CIGS and thus protects the layer 12 during the deposition of the layer 14.
• FIG. 1 d illustrates a step of implementing the method in which another etching is performed, either mechanically or by laser ablation.
• This etching corresponding to step P2 mentioned above, consists of removing all the layers previously deposited on the 1 1 layer of molybdenum. This etching thus makes it possible to make an aperture referenced 1 1 1 in FIG. 1 d. It will make it possible to carry out a portion (P2) of the electrical interconnection between two adjacent cells.
• the width of the opening 1 1 1 is generally between 50 ⁇ m and 150 ⁇ m and is preferably equal to about 100 ⁇ m.
• the distance between the openings 110 and 111 is generally between 50 pm and 150 pm and is preferably equal to about 00 pm.
• FIG. 1e illustrates yet another step of implementing the method, in which a layer of a transparent conductive oxide 15 is deposited.
• This layer may be deposited by sputtering and have a thickness of a few hundred nm.
• It may especially be Al doped ZnO having a thickness of about 500 nm.
• This Al doped ZnO layer will be used to form a conductive transparent electrode referenced 15a for the front face electrode of the cell 2 and 15b for the front face electrode of the cell 3 (see FIG. 1f).
• the n-type semiconductor layer 13 may have discontinuities.
• the ZnO layer 14 then has the function of providing electrical insulation between the transparent conductive layer 15 and the layer 12 of CIGS.
• ITO tin-doped indium oxide
• silver nanowires silver nanowires
• carbon nanotubes could also be used to make this transparent conductive electrode.
• other deposit techniques could also be used.
• the distance between the openings 110 and 111 must be large enough to avoid a too great interconnection resistance between the front face electrode 15a of the cell 2 and the rear face electrode 11b of the cell 3.
• FIG. 1f illustrates a last step of the method, in which another etching is performed in the stack of layers, in order to definitively isolate the cell 2 from the cell 3.
• This etching step corresponds to the step P3 mentioned above. It can be performed mechanically or by laser ablation and consists in removing all the layers deposited on the rear face electrode 11b.
• the opening 112 obtained makes it possible to electrically isolate the two cells 2 and 3 at their front face electrodes 5a and 15b.
• the opening 112 more generally has a width of between 10 ⁇ and 200 ⁇ , and is preferably of the order of 100 ⁇ m.
• Figure 1f also illustrates the path of the charges between the two adjacent cells 2 and 3.
• the front face electrode 15a of the first cell 2 makes it possible to collect on the front face the electric charges generated in this cell 2 and to route them towards the rear face electrode 11b of the adjacent cell 3.
• Their object is to locally increase the conductivity of the CIGS material in order to conduct the conduction of the charges from the front face electrode of a given cell to the back-face electrode of the adjacent cell.
• the invention therefore aims to overcome the disadvantages of this type of etching by proposing another method for electrically isolating two adjacent cells at their backside electrodes.
• the invention relates to a method for producing a photovoltaic module comprising a plurality of solar cells in a thin-film structure, in which are successively realized in the structure, an electrode on the rear face, a photovoltaic layer obtained by annealing at from metal precursors deposited in the form of a layer, and another layer of semiconductor to create a pn junction with the photovoltaic layer, the method also consisting in making etchings in the different layers of the structure.
• the deposition of the precursor layer is carried out in a localized manner, so as to leave at least one zone of the backside electrode located between two adjacent cells free, the annealing modifying this zone which has a higher resistivity important than the rest of the back-side electrode, so as to provide electrical isolation between the back-face electrodes of two adjacent cells.
• the precursors comprise metal precursors which are of Cu, In and Ga or Cu, Zn and Sn type.
• the annealing is advantageously carried out at a temperature of between 400 ° C. and 600 ° C. and preferably of the order of 550 ° C.
• the area of the backside electrode, located between two adjacent cells and having a higher resistivity, may be in the form of a band. This typically has a width of 100 ⁇ .
• the deposition of the precursor layer is advantageously carried out by screen printing or slit-coating.
• the invention also relates to a photovoltaic module comprising a plurality of solar cells connected in series on a common substrate, each cell comprising a front electrode, transparent to light, and a rear-end electrode spaced from the electrode on the front face by a photovoltaic layer and another layer of semiconductor to create a pn junction.
• the backside electrodes of two adjacent cells are electrically insulated by a region of the electrode. rear face which is located between the two cells and which has a greater resistivity than the rest of the back-side electrode.
• the photovoltaic layer comprises a discontinuity in the region of the back-face electrode situated between two adjacent cells and having a higher resistivity than the rest of the back-side electrode.
• the photovoltaic layer is preferably made of CIGS or CZTS.
• the electrode on the rear face is advantageously made of molybdenum.
• the area of the back-face electrode situated between two adjacent cells and with a higher resistivity has a width of between 50 ⁇ m and 150 ⁇ m and is in particular equal to approximately 100 ⁇ m.
• FIGS. 2a to 2g All these figures are sectional views and show different stages of implementation of the method according to the invention.
• Figure 2a shows a substrate 4 which can be made of various materials, typically glass, plastic or metal.
• this substrate is made of soda-lime glass whose thickness is a few millimeters and, for example, 3 mm.
• a molybdenum layer 41 On this substrate 4, is deposited a molybdenum layer 41 whose thickness is between 100 nm and 2 pm and which is, for example, equal to 500 nm.
• the deposition of the molybdenum layer may in particular be carried out by sputtering.
• the metal layer will be used to constitute the electrode on the rear face of the different cells of the photovoltaic module that will be obtained by the method according to the invention. Unlike conventional monolithic interconnection methods, no etching step is performed in the layer 41. In other words, in the context of the invention, the step P1 is absent.
• FIG. 2b illustrates the stage of the process in which the precursors are brought which will lead to the formation of the photovoltaic layer, so as to constitute the layer 42.
• the photovoltaic layer will then be made of a CIGS type material.
• the following ratios are preferably respected:
• Metal precursors can also be of the type
• the metal precursors are preferably deposited in such a way that the following ratios are respected:
• the method according to the invention then leads to obtaining solar cells whose photovoltaic layer is made of material of the CZTS type and, in particular, Cu 2 ZnSnSe 4 , Cu 2 ZnSnS 4 or Cu 2 ZnSn (S, Se) 4, depending on whether the layer 42 comprises selenium, sulfur or a mixture of the two components.
• the germanium may also be integrated into the CZTS mesh to form a Cu 2 Zn (Sn, Ge) material (S, Se) 4 , when the layer 42 comprises a mixture of selenium and sulfur.
• the metallic constituents can also be of the type
• the method according to the invention then leads to obtaining solar cells whose photovoltaic layer is made of a material of the Cu (ln, Al) (S, Se) 2 type .
• FIG. 2b illustrates a layer 42 which is not deposited continuously on the back-face electrode 41.
• zones 420 are totally devoid of constituents, the layer 41 then being bare at these zones 420.
• these zones 420 are presented, in plan view, in the form of strips, intended to separate two adjacent cells of the photovoltaic module. These strips have a width of between 50 ⁇ and 150 ⁇ m and in particular equal to 100 ⁇ m.
• these areas will form a complementary network of the cell network.
• This layer 42 may comprise essentially metal precursors.
• the sulfur or selenium is then brought later in gaseous form. They can also be made in the form of a continuous layer deposited on the discontinuous layer of metal precursors.
• the layer 42 can comprise both metal precursors and selenium or sulfur.
• Various deposition methods can be implemented to produce the layer 42. It can in particular be obtained by using a silkscreen frame having the pattern corresponding to the zones 420, through which an ink comprising metal precursors and, depending on the case, the sulfur or selenium, is deposited. The deposit is therefore made in a localized manner.
• FIG. 2c illustrates the next step of the method according to the invention in which the metallic constituents are converted into a layer 46 of semiconductor material, for example CIGS or CZTS.
• the conversion of metal precursors into CIGS by the addition of Se or S is conventionally carried out by annealing at high temperature. It is called selenization annealing in the case of selenium or sulfurization annealing in the case of sulfur.
• Selenium or sulfur can be supplied during annealing in gaseous form or, before annealing, during the deposition of a continuous layer on the discontinuous layer of metal precursors or during the deposition of the layer of metal precursors. In the latter case, the annealing is carried out under a neutral atmosphere.
• This annealing may typically be carried out at a temperature between 400 ° C and 600 ° C and preferably equal to 550 ° C.
• the duration of the annealing is generally between 30 s and 30 min and is preferably of a duration of about 1 min.
• the zone 410 of the back-face electrode 41 is directly exposed to the input of selenium or sulfur, depending on the annealing mode employed (Se metal vapor supply or S, gas H 2 Se or H 2 S, or deposition of a layer of Se or S).
• the selenium will react with the molybdenum layer 41 to form MoSe 2 in the zone 410.
• the MoSe 2 grows in a compact hexagonal structure whose axis c is parallel to the surface of the layer 41.
• the planes perpendicular to the axis c form leaflets.
• it is the sulfur present in the layer 42 or brought independently that will diffuse and react with the underlying molybdenum layer to form MoS 2 .
• the thickness of the Mo layer and the minimum amount of selenium or sulfur, provided in various forms, will be adjusted so that the Mo is transformed into MoSe 2 or MoS 2 throughout its thickness.
• This minimal amount of selenium or sulfur is conventionally referred to as the "equivalent thickness" of selenium or sulfur, that is to say the thickness of a deposited layer of selenium or sulfur exactly corresponding to the stoichiometry of MoSe 2 or MoS 2 so that the Mo layer is converted to MoSe 2 or MoS 2 throughout its thickness.
• a layer of Mo with a thickness of 500 nm can thus be converted into a layer of approximately 1.95 ⁇ m of MoSe 2 with an equivalent thickness of 1.7 ⁇ m in the case of selenium or 1.75 ⁇ m in the case of case of sulfur.
• the zone 410 of the back-face electrode 41 which is not in contact with the metal precursors is transformed during the annealing, thanks to the contribution of selenium or sulfur.
• the resistivity of MoSe 2 or MoS 2 in the direction parallel to the c axis is much greater than that of molybdenum. Indeed, the resistivity ratio is greater than 10 8 .
• the zone 410 of the electrode on the rear face 41 thus has a higher resistivity than the rest of the electrode on the rear face 41.
• this area 410 of the rear-facing electrode 41 having a higher resistivity thus makes it possible to avoid the etching step P1 and thus to eliminate the disadvantages associated with this etching step.
• the annealing may also be accompanied by the formation of a layer of MoSe 2 at the interface of the layers 41 and 42 (not shown in the figures).
• this layer is thin, especially less than 300 nm. It adds only a small resistance insofar as the flow of the charges between the layers 41 and 42 is effected in the direction perpendicular to the axis c of the MoSe 2 layer. However, in this direction, the resistivity of MoSe 2 is very low. It also forms an ohmic contact that improves the electrical properties of solar cells.
• FIGs 2d to 2g describe the other steps of the method according to the invention, which are similar to those described with reference to Figures 1c to 1f.
• Figure 2d shows an implementation step in which a layer 43 of n-type semiconductor is deposited on the layer 46, to form the pn junction.
• the material used may be CdS, ZnS or ZnOS.
• FIG. 2d illustrates another step of the method which is optional and which consists in depositing a layer 44 of a transparent material on the layer 43.
• the material used may be ZnO.
• Figure 2e illustrates an etching step corresponding to step P2 mentioned above. It consists in removing all the layers previously deposited on the backside electrode 41b, however away from the zone 410 of higher resistivity.
• This etching thus makes it possible to make an opening referenced 411 in FIG. 2e, and thus a portion of the electrical interconnection between the two adjacent cells referenced 5 and 6 in FIG. 2g.
• the zone 410 and the opening 411 are located at a minimum distance of between 50 ⁇ m and 150 ⁇ m, and in particular of the order of 00 ⁇ m.
• FIG. 2f illustrates another implementation step, in which a layer of a transparent and conductive oxide 45 is deposited on the layer 44 or directly on the layer 43 when the layer 44 is omitted.
• FIG. 2g illustrates a last step of the method, in which another etching is performed in the stack of layers.
• This etching step corresponds to step P3.
• the opening 412 obtained is further removed from the zone 410 than the opening 411. It makes it possible to electrically isolate the two cells 5 and 6, at their front face electrodes 45a and 45b.
• the two cells 5 and 6 are spaced from each other by the zone 410 and the openings 411 and 412. This space is the interconnection zone.
• Figure 2g also illustrates the path of the charges between two adjacent cells 5 and 6.
• the front face electrode 45a of the first cell 5 makes it possible to collect, on the front face, the electric charges generated in this cell 5 and to route them towards the rear face electrode 41b of the adjacent cell 6.
• the method which has just been described has the advantage of eliminating one of the etching steps conventionally provided for in the monolithic interconnection processes, in this case the step P1, and thus of being able to overcome the disadvantages associated with it. at this stage of engraving.

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