Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
  • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
  • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
  • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body

Definitions

• the present invention relates to high-mobility electronic field effect transistors referred to as HEMT transistors, an acronym for "High Electron Mobility Transistor", in the English language.
• the present invention more specifically relates to the stacks from which are manufactured the HEMT transistors used as a low noise or power amplifier, as a switch or as an oscillator and covering the frequency range typically between 1 MHz and 100 GHz. And more particularly the protective layer of the upper face of the stack called "passivation layer".
• passivation layer is understood to mean a layer of material disposed on the top face of the stack intended to protect the component against corrosion, mechanical wear, chemical attack and condition the surface charge states.
• FIG. 1 represents a sectional view of the structure of a conventional elementary HEMT transistor system, in a xOz plane, made on a substrate 11.
• an insulating or semiconductor substrate 11 comprising, for example, silicon (Si), Silicum carbide (SiC) or Sapphire (Al 2 O 3 ), on which is produced an Emp stack along the z axis of at least two semiconductor layers which extend into the xOy plan.
• the buffer layer 12 comprises, for example, a material comprising a binary compound of nitrogen, such as GaN or a ternary compound of III nitride, called III-N, such as AIGaN, or more precisely the Al x Ga 1-x N.
• III-N such as AIGaN
• the thickness of the buffer layer 12 along the z axis is between 0.2 microns and 3 microns.
• a second layer, called a barrier layer 13 has a larger forbidden band than that of the buffer layer 12.
• This barrier layer 13 comprises a material based on quaternary compound, ternary or binary element III nitride, called III-N, based on Al, Ga, In or B. Typically, the thickness of the barrier layer 13 is between 5 nm and 40 nm.
• the barrier layer 13 may comprise Al x Ga 1-x N or ⁇ 1-x ⁇ ⁇ ⁇ , or an In 1-x AI X N / AIN or Al x Ga 1-x N / AIN.
• the bandgap widths of Al x Ga 1-x N and ln 1-x Al x N vary between 3.4eV (GaN) and 6.2eV (AIN) and between 0.7eV (InN) and 6.2eV (AIN), respectively.
• the buffer layer 12 and the barrier layer 13 are conventionally produced by organometallic vapor phase epitaxy, better known under the term MOCVD, the acronym for "Metalorganic Vapor Phase Epitaxy", in the English language, or by molecular beam epitaxy, better known by the term “MBE”, acronym for "Molecular Beam Epitaxy", in the English language. Additional layers may be present on the upper face 14 of the stack Emp including a passivation layer 16.
• An HEMT transistor conventionally comprises a source S, a drain D and a gate G deposited on the upper face 14 of the stack Emp.
• a gate G is deposited between the source S and the drain D and makes it possible to control the transistor.
• the conductance between the source S and the drain D is modulated by the electrostatic action of the gate G, typically of the Schottky type or of the MIS type, acronym for metal / insulator / semiconductor, and the voltage V GS applied between the gate G and the source S controls the transistor.
• the gate G typically of the Schottky type or of the MIS type, acronym for metal / insulator / semiconductor
• These electrons are mobile in the xOy plane and have a high electron mobility ⁇ , typically the electron mobility ⁇ e is greater than 1000 cm 2 / Vs.
• a potential difference V DS is applied between the source S and the drain D, with typically a source S at ground, and the value of the current IDS is a function of the applied voltage V GS between the gate G and the source S.
• the transistor effect is based on the modulation of the conductance gm between the contacts of the source S and the drain D by the electrostatic action of the control electrode G. The variation of this conductance is proportional to the number of carriers free in the channel, and therefore the current between the source S and the drain D.
• FIG. 2 represents the distribution of the electric charges in the vicinity of the heterojunction 15.
• the buffer layers 12 and barrier 13 comprise materials of the family of 11-N highly electronegative.
• a fixed electrical charge appears at their interface, which may be positive ⁇ + as shown in FIG. 2, or negative ⁇ -.
• This fixed charge attracts mobile charges: the electrons when it is positive as in Figure 2, or the holes when it is negative. It is these mobile charges em which create a current when a voltage is applied between the drain D and the source S.
• the HEMT structure comprising a GaN type buffer layer 12 in particular has the particularity of having the two-dimensional gas 9 close to the upper face 14 of the stack Emp, typically at a distance of between 2 and 30 nm.
• This two-dimensional gas 9 is generated by the equilibrium of the electric charges in the Emp stack. It is, consequently, completely dependent on the electric charges present on the upper face 14 of the stack Emp, and, more specifically, on the electrical charges present at the interface 17 between the upper face 14 of the stack Emp and the passivation layer 16.
• the two-dimensional gas 9 comprises electric charges, in this case electrons, these electric charges are partly the image of the charges present on the surface of the stack Emp.
• the two-dimensional gas 9 has a surface charge density of 10 13 electrons, cm -2 , which also corresponds to the surface charge density of the upper face of the stack Emp.
• a function of the passivation layer 16 is to fix the surface state on the upper face 14 of the stack Emp, and whatever the conditions of use of the transistor, the voltage applied between the source S and the gate G, in a configuration that minimizes the traps in the deep electrical centers so as to obtain a current close to the maximum current during the entire operation time of the transistor.
• Called deep center an impurity whose energy level is set to more than 2 to 3 times the thermal activation energy (3/2 k b * T) of the minimum of ia conduction band for an N-type impurity or at most of the valence band for a P-type impurity.
• the thermal activation energy is of the order of 40 meV.
• a center will therefore be considered deep when it is located at more than 100 meV of one of these extrema, which is the case for GaN doped with acceptor-type impurities.
• These centers are negatively charged when the transistor is turned on and as they are deep do not discharge at operating frequencies above megahertz. This has the effect of reducing the number of mobile charges em present in the conductive channel, which reduces the current.
• the passivation layer 16 comprises a monolayer of material, typically comprising silicon nitride (SiN) or silicon oxide (SiO 2 ) making it possible to reduce the trapping effects at the interface 17 between the upper face 14 of the stack Emp and the passivation layer 16.
• This passivation protects ('stacking Emp of semiconductor materials, for aggressive operating conditions, as for high electric fields, greater than 6.10 6 V / cm and high operating temperatures above 300 ° C.
• FIG. 3a shows a profile of a transistor comprising a passivation monolayer 16 according to the known art on the surface of the upper face 14 of the stack
• FIG. 3b is an enlargement of the base of the gate G or else referred to as a grid foot framed in Figure 3a.
• the upper face 14 of the stack comprises a source S, a gate G, and a drain D.
• FIG. 4a corresponds to a mapping of the intensities of the electric field on the profile represented in FIG. 3b in the vicinity of the gate foot G when a voltage V DS of 20V is applied and that a drain current I DS of 200 mA per mm of grid length Lg.
• the values of the intensity of the electric field are represented by gray levels, the areas for which the intensity of the electric fields is important are represented in light gray and the zones of lower intensity of electric fields are represented in dark gray. In other words, the higher the intensity of the electric field, the more clearly the area is represented.
• two zones Z1; Z2 can be highlighted: a first zone Z1 of high intensity of electric field disposed at the foot of the gate G between the gate G and the drain D over a distance of about 0.15 microns from the base of the grid G, the intensity of the electric field on this first zone Z1 of high electrical intensity being between 3.75.10 6 V.cm -1 and 5.10 6 V.cm -1 , and a second zone Z2 of lower field strength electric extending from the first zone Z1 of high intensity and extending over the remainder of the upper face 14 on which the intensity of the electric field is less than 1.10 6 V.cm -1 .
• FIG. 4b is a map of FIG. 3b showing the intensity of the electric field when a negative bias is applied to the gate G preventing the two-dimensional gas 9 from flowing.
• the electric potential difference V GS between the gate G and the source is -6V.
• the first zone Z1 of high intensity is larger than previously, it is located from the base of the grid G and extends over a distance of 0.25 microns.
• the portion of the first zone Z1 of high intensity in direct contact with the gate G has an electric field strength greater than 5.10 6 V.cm -1 .
• the intensity of the electric field then decreases progressively as one moves away from the base of the gate G to reach values lower than 2.5 ⁇ 10 6 V.cm -1 at a distance of 0.12 ⁇ m from the base of the gate G.
• the remainder of the passivation layer 16 has electric field strengths of less than 2.5 ⁇ 10 6 V.cm -1 .
• FIGS. 5 and 5 are simulations of the evolution of the electric field as a function of the distance with respect to the gate foot G.
• FIG. 5a shows the simulated curves 31 and 32 of intensity of the electric field as a function of the distance from the base of the grid at 5 nm from the surface of the stack Emp, ie inside of the passivation monolayer produced according to the known art, respectively for a pinched transistor not allowing the moving charges of the two-dimensional gas 9 to circulate, and for an open transistor allowing the electrons to circulate.
• the curve 31 is a simulated graphical representation of the intensity of the electric field as a function of the distance for a zero voltage V DS and a voltage V GS equal to -5V. In other words, it is the estimation of the electric field when the transistor is pinched, that is to say, when the two-dimensional gas is depopulated under the gate.
• the intensity of the electric field decreases as one moves away from the gate G. It decreases rapidly near the gate foot and then decreases more slowly. Indeed, in contact with the gate G, the intensity of the electric field is 7.2.10 6 V / cm, the intensity is reduced by half at a distance of 0.025 microns from the gate foot G. At a distance 0.3 ⁇ m of the gate foot, the intensity of the electric field is only 10 6 V / cm.
• the curve 32 is a simulated graphical representation of the intensity of the electric field as a function of the distance for a zero V DS voltage and a zero V GS voltage, the current DS measured being 200 mA / mm.
• the two-dimensional gas 9 flows in the channel.
• the curve 32 has a similar appearance to the curve 31.
• the intensity of the electric field is 5.10 6 V / cm and then decreases rapidly when moving away from the gate foot.
• FIG. 5b shows simulated curves 33 and 34 of intensity of the electric field as a function of the distance with respect to the gate foot G inside the channel.
• Curve 33 is a simulated graphical representation of the intensity of the electric field inside the channel, that is to say along a plane buried in the stack contrary to the case of curves 31 and 32 of FIG. 5b. This simulation of electric field is a function of the distance from the gate foot G for a zero V DS voltage and a voltage V GS equal to -5 V when the transistor is pinched.
• the intensity of the electric field in the channel vis-à-vis the gate foot reaches a value of 3.5.10. 6 V / cm. This value is twice as small as the estimated value at the extreme surface ( Figure 5a). This value then decreases rapidly with distance.
• curve 33 is an estimate of the electric field strengths in the channel as the two-dimensional gas is flowing in.
• the intensity of the electric field in the channel opposite the gate foot reaches a value of 2.5 ⁇ 10 6 V / cm.
• the surface state of the upper face 14 of the stack Emp can then be modified in particular by the hydroxide ions present in the surrounding atmosphere.
• an object of the invention is to provide a passivation layer that notably improves the performance of the transistor.
• a field effect transistor comprising:
• a stack (Emp) along the z-axis of semiconductor materials comprising a binary or ternary or quaternary nitride compound; o a drain (D), a source (S) and a grid (G); a passivation tray (16) disposed above the top face (14) of said stack (Emp), said passivation layer (16) comprising two sub-layers (16a; 16b);
• drain (D), said source (S) and said gate (G) define:
• said first sub-layer (16a) extends over the second zone (Z2), comprises a first material (Mat1) of electric breakdown field E c ii ii, the electric charge of said first sub-layer (16a) being strictly less than the electrical charge of said upper face (14) of the stack (Emp);
• said second sub-layer (16b) extends over (a first zone (Z1), covers the first sub-layer (16a), and comprises a second material (Maté) electric breakdown field E cl2 strictly greater than E cl1
• the electrical breakdown field of the second material Mat2 is greater than the maximum electric field at the base of the gate foot.
• the synthesis temperature T synth of the second material Mat2 is greater than the maximum temperature T Z1 reached on the first zone Z1 during operation of the transistor.
• the charge of said first sublayer 16a of the transistor is less than or equal to 1% of the load of said upper face 14.
• synthesis temperature of the second material is meant the temperature reached during the preparation of the material.
• the production of a passivation layer comprising at least two sub-layers makes it possible to fulfill the functions of stabilizing the surface state and protecting the surface of the stack against aggressive use conditions such as a high electric field or high temperatures.
• the residual charge density of the first material is less than or equal to 1% of the surface charge density of the upper face.
• the thickness of the first sub-layer in the direction of the z axis is greater than or equal to 20 nm.
• the first material comprises SiN silicon nitride or Al 2 O 3 alumina.
• the first material is obtained by inductively coupled plasma-phase physical deposition (ICP-CVD) or atomic layer deposition (ALD).
• This manufacturing method makes it possible to deposit the silicon nitride atomic layer by atomic layer, which makes it possible to obtain a material of high purity, which is poor in oxygen, in particular, which limits the reactivity at the surface of the first underlayer.
• the first underlayer thus formed is stable over time.
• the second material comprises silicon nitride SiN or silicon oxide or aluminum nitride obtained by chemical vapor deposition-assisted plasma (PECVD) or by cathode sputtering or by atomic layer deposition (ALD ).
• PECVD chemical vapor deposition-assisted plasma
• ALD atomic layer deposition
• the thickness of the second sub-layer in the direction of the z axis is greater than or equal to 50 nm so as to encapsulate the first sub-layer and to move the surface of the first underlayer away from the atmosphere. surrounding.
• the synthesis of the first material is performed by a method modifying only the first and second atomic layer of the upper face of the stack.
• the synthesis of the first material is carried out by inductively coupled plasma-phase physical deposition (ICP-CVD) or atomic layer deposition (ALD).
• ICP-CVD inductively coupled plasma-phase physical deposition
• ALD atomic layer deposition
• the synthesis temperature of the second material is greater than the maximum temperature observed on the first zone when the transistor is in operation.
• the synthesis of the second material is carried out by a plasma-assisted physical vapor deposition (PECVD) method.
• PECVD plasma-assisted physical vapor deposition
• FIG. 1 already cited schematically represents a section of the structure of a conventional HEMT transistor
• FIG. 2 already cited represents the distribution of the charges in the vicinity of the heterojunction of the conventional HEMT transistor
• FIG. 3a schematically represents a profile of the stack Emp
• FIG. 3b is an enlargement of the box framed on FIG. 3a situated at the base of the grid
• FIGS. 4a and 4b are maps of the electric field intensities at the base of the gate, respectively, when the transistor is in operation (curves 32 and 34) and when the transistor is pinched (curves 31 and 33).
• FIGS. 5a and 5b show simulated curves of the intensity of the electric field as a function of the distance
• FIG. 6 is a schematic representation of the passivation layer, according to the invention.
• FIGS. 7a and 7b show characterization curves of the transistors respectively, with a passivation layer according to the known art, and, with a passivation layer, according to the invention.
• FIG. 6 is a schematic representation of the profile of a stack comprising a passivation layer according to the invention.
• the stack Emp comprises a superposition of layers of semiconductor materials.
• the stack Emp comprises in particular a substrate 11, a buffer layer 12 and a barrier layer 13.
• a source S On the upper face 14 of the stack Emp are arranged a source S, a gate G and a drain D.
• the upper face 14, the gate G, the source S and the drain D are covered with a passivation layer 16 according to the invention.
• the barrier layer 13 may comprise InAIGaN, AIGaN or ⁇ .
• the indium, gallium and nitrogen atoms are particularly unstable and can easily react with the molecules of the surrounding atmosphere, which modifies the surface state of the upper face 14 of the stack Emp, and which consequently modifies the flow of two-dimensional gas 9 in the channel. Indeed, as we have already mentioned above, the two-dimensional gas 9 is dependent on the surface state of the upper face 14 of the Emp stack, in particular.
• the idea of the invention therefore consists in disposing a passivation layer on the surface of the upper face 14.
• the passivation layer comprises two different materials so as to fulfill the two different functions of the passivation layer 16.
• the passivation layer 16 comprises two sub-layers 16a; 16b: a first sub-layer 16a comprising a first material Mat 1 disposed on the second zone Z2 of the upper face 14 of the stack Emp intended to encapsulate the surface of the stack so as to freeze the surface state, and a second sub-layer 16b disposed on the first zone Z1 of the upper face 14 of the stack Emp and on the first sub-layer 16a, the second sub-layer 16b comprising a second material Mat 2 intended to protect the upper face 14 of the stack of high intensities of electric field, in particular.
• the first material Mat 1 comprises silicon nitride SiN, or ⁇ 2 ⁇ 3 obtained by deposition methods such as ALD, acronym for "Atomic Layer Deposition", in the English language, and deposit of atomic layer, in French language
• This method makes it possible in particular to produce an atomic layer deposition per atomic layer making it possible to obtain a deposit of the first dense and low-reactivity material Mat 1. Nevertheless, the use of ALD does not imply obtaining a dense and unreactive material: these characteristics can be variable depending on the setting of the deposit, chosen in the embodiments of the invention to be adapted to the manufacture of a dense and unreactive material. However, other deposit methods described as "soft" for producing a dense, low-reactivity deposit can be envisaged, such as ICP-CVD acronym for inductively coupled chemical vapor phase-plasma deposition.
• soft deposit method means methods that modify at most the extreme surface of the material on which the deposit is made. Typically the extreme surface corresponds to one or even two atomic layers. Preferentially, a gentle deposition method does not modify the surface of the material on which the deposit is made.
• the underlayer 16a thus produced has an electric charge strictly less than the electric charge of the upper face 14 of the stack Emp (that is to say a surface charge) and more specifically to the electric charge of the upper surface. 14 in contact with said sublayer 16a.
• the electric charge of the sublayer 16a is less than a few percent of the electric charge of the two-dimensional gas 9, and more specifically less than or equal to 10% and preferably less than 1%.
• the electric charge of the two-dimensional gas 9 is a function of the electric charge on the upper surface 14 and is substantially equal to the electric charge on the upper surface 14.
• the charge of said first sublayer is less than or equal to 10% of the load of said upper face 14 and preferably less than or equal to 1% of the load of said upper face 14.
• the surface density of charge mat1 ⁇ of the underlayer 16a is preferably between 10 10 and 10 12 charges.cm -2 .
• the thickness of the first sub-layer 16a in the direction of the stack Emp is greater than 20 nm so as to freeze the surface state of the upper face 14 of the stack Emp.
• the second sub-layer 16b comprises a second material Mat 2 resistant to high electric field strengths and high temperatures above 200 ° C, the second sub-layer 16b being disposed on the first zone Z1 of high intensity. and on the first underlayer 16a.
• the second material Mat2 comprises silicon nitride SiN, silicon oxide Si0 2 or aluminum nitride AIN obtained by PECVD, acronym for plasma-enhanced chemical vapor deposition or by sputtering or deposition of ALD atomic layers and heat treatment.
• PECVD plasma-enhanced chemical vapor deposition or by sputtering or deposition of ALD atomic layers and heat treatment.
• the parameters of an ALD deposition of a layer of Mat2 material will be different from those potentially used for the deposition of a Mat1 material layer.
• the breakdown electric field ⁇ cl2 of the second sub-layer 16b is strictly greater than the breakdown electric field E cl1 of the first sub-layer 16b. layer 16a.
• the deposition methods of the sub-layers 16 are chosen to allow, among other things, this inequality.
• the thickness above the first sub-layer 16a in the direction of the stack Emp of the second sub-layer 16b is greater than 50 nm so as to move the surface of the first sub-layer 16a away. surrounding atmosphere.
• FIGS. 7a and 7b show the characterization curves of the transistors for different gate voltage values, respectively for a transistor comprising a passivation monolayer according to the prior art and a passivation layer according to the invention.
• FIG. 7a shows transistor characteristic curves comprising a passivation monolayer according to the known art. The measurements taken for different resting points make it possible to quantify the effects of charges.
• the gate voltage V G is -5V.
• FIG. 7b represents the transistor characteristic curves comprising a passivation multilayer according to the invention.
• the maximum drain current I D of a transistor comprising a multilayer passivation layer according to the invention is greater than the drain current of a transistor comprising a monolayer passivation layer according to the invention. known art.
• a passivation layer according to the invention thus makes it possible to freeze the surface state of the upper face of the stack and thus to confine the two-dimensional gas in the channel by avoiding the trapping of the electrons in deep centers.
• the passivation layer according to the invention makes it possible to protect the stack from high electric field strengths and high temperatures.
• the performance of a transistor comprising a passivation layer according to the invention is improved.

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