EP3268989A1 - Module de semi-conducteur de puissance pourvu d'une structure de connexion par soudage améliorée - Google Patents

Module de semi-conducteur de puissance pourvu d'une structure de connexion par soudage améliorée

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Publication number
EP3268989A1
EP3268989A1 EP16708666.9A EP16708666A EP3268989A1 EP 3268989 A1 EP3268989 A1 EP 3268989A1 EP 16708666 A EP16708666 A EP 16708666A EP 3268989 A1 EP3268989 A1 EP 3268989A1
Authority
EP
European Patent Office
Prior art keywords
power semiconductor
bond
bonding
connection
feet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP16708666.9A
Other languages
German (de)
English (en)
Inventor
Reimund Pelmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Bipolar GmbH and Co KG
Original Assignee
Infineon Technologies Bipolar GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Bipolar GmbH and Co KG filed Critical Infineon Technologies Bipolar GmbH and Co KG
Publication of EP3268989A1 publication Critical patent/EP3268989A1/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/528—Multiple bond wires having different structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/533—Cross-sectional shape
    • H10W72/534—Cross-sectional shape being rectangular
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5438—Dispositions of bond wires the bond wires having multiple connections on the same bond pad
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a power semiconductor module.
  • Power semiconductor modules are semiconductor devices that are used in power electronics circuits. Power semiconductor modules are commonly used in automotive and industrial applications, such as in inverters and rectifiers.
  • the semiconductor components included in the power semiconductor modules are usually IGBT (Isolated Gate Bipolar Transistor) semiconductor chips or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor chips.
  • IGBT and MOSFET semiconductor chips have varying nominal voltages and powers.
  • Some power semiconductor modules also have additional semiconductor diodes (i.e., freewheeling diodes) in the semiconductor package for overvoltage protection.
  • a power semiconductor module usually has one or more power semiconductor components, also referred to below as power semiconductors, on a single substrate.
  • the substrate typically includes at least one insulating ceramic substrate, such as Al 2 O 3 , AlN, Si 3 N 4, or other suitable material to electrically isolate the power semiconductor module.
  • the substrate is usually applied to a metallic base plate serving as a substrate stabilizing support for mechanical attachment and thermal coupling of the module to a heat sink.
  • At least one top of the ceramic substrate is metal coated with either pure or plated Cu, Al, or other suitable material to contact the power semiconductor disposed thereon and soldered thereto on a regular basis, and to provide electrical potential areas, particularly load potential areas.
  • these potential surfaces serve to supply or remove electricity via so-called bond connections to the power semiconductor, on the other hand, mechanical fastening and electrical connection with connection parts, which supply or remove power to or from the module, in particular from its housing, for example to the latter outside the housing with external conductors to connect, for example by means of screwing.
  • the metal layer provided for the potential areas is usually bonded to the ceramic substrate by means of direct copper bonding (DCB), direct aluminum bonding (DAB) or active metal brazing (AMB) techniques.
  • bonding connections for electrical connection of the potential surfaces with the at least one terminal surface of the respective power semiconductor facing away from the substrate, there are regularly provided bonding connections in the form of bonding wires, also referred to as a wire bond connection, or bonding tapes also called a belt bond, which electrically conducts the conductive connection Establish contact between the potential surface and the pad of the semiconductor.
  • bonding wires also referred to as a wire bond connection
  • bonding tapes also called a belt bond
  • thermocompression bonding in short: TC bonding
  • TS bonding Thermosonic-Ball-Wedge- bonding
  • US bonding ultrasonic wedge -Wedge bonding
  • This solder connection of the second main area of the power semiconductor component forms part of the current supply or removal. Further current connections are made by means of wire bonds between the metallization of the first main area of the power semiconductor component providing the connection area and a load potential area. Characteristic of the known wire bond connections is that the bonding wires are arranged closely adjacent to each other, and that the bonding feet of the individual bonding wires, especially on the power semiconductor component, are arranged in a row or slightly offset. According to the prior art, power semiconductor components are contacted not only by means of individual juxtaposed bonding wires for power supply, but often with two or more in the direction of the bonding wires at least partially superposed bonding wires. The individual bonding wires frequently also contact the connection surface thereof by means of a plurality of bonding feet in order to improve the current distribution on the power semiconductor component.
  • Simulations show that in an arrangement of the bonding wires between a load terminal potential surface and a power semiconductor device according to the prior art, the current is fed inhomogeneously via the pad in the power semiconductor device and thus this is not burdened evenly in its entire surface for power management.
  • DE 10 2005 039 940 B4 discloses a wire bond connection in which the second bond feet of a plurality of bond connections are distributed over the entire connection surface in a checkerboard pattern and the bond connections form two groups of several bond connections, the groups differing in the length of the bond connections and the second bond legs are not define a common segment or no common area on the pad.
  • a disadvantage of this embodiment of a wire bond is that in this case a sufficiently large pad of the power semiconductor device must be available in order to use such complex topologies meaningful.
  • surge current loads of this power semiconductor component are to be considered in particular. These surge currents exceed the continuous load of the power semiconductor component by a multiple in the order of tenths of a second in a short period of time. In this case, designs of bond connections designed for continuous operation are not necessarily advantageous.
  • the present invention has for its object to provide a bond for power semiconductor modules, wherein the maximum current carrying capacity of Bond connection in its entirety, especially at surge load, is improved, in particular the current distribution and thus the heat distribution over the individual bonds is balanced.
  • This object is achieved by a power semiconductor module having the features of claim 1.
  • particularly advantageous embodiments of the invention disclose the dependent claims. It should be noted that the features listed individually in the claims can be combined with each other in any technically meaningful manner and show further embodiments of the invention. The description additionally characterizes and specifies the invention, in particular in connection with the figures.
  • the power semiconductor module according to the invention has a substrate, preferably an electrically insulating substrate. For example, it is a ceramic substrate, such as Al 2 0 3 , AIN, Si 3 N 4 .
  • the substrate is preferably arranged on a metallic base plate, wherein the base plate is designed for arrangement and optionally attachment to a heat sink.
  • at least one power semiconductor is further provided.
  • the power semiconductors considered here are, for example, uncontrolled components such as power diodes, or also controlled components such as power thyristors or power transistors, such as a bipolar transistor. These controlled components have to drive them at least one further connection surface provided in general by a metallization provided on its first main surface, which is electrically separated from the load current conducting and is also connected to a control potential surface of the substrate by means of a bonding connection according to the prior art , This bond between the control or the control terminals is not the subject of the invention.
  • the power semiconductor has a connection surface on its side facing away from the substrate.
  • the pad can be formed as a continuous metallization or segmented, as it may be the case for example in the emitter pads of an IGBT.
  • an optionally segmented load potential area arranged on the substrate next to the power semiconductor is furthermore provided.
  • each of the plurality of bonding connections has at least one first type of bonding foot, in short the first bonding foot, wherein the first bonding foot is characterized in that the one on the at least one load potential surface is arranged.
  • each of the plurality of bonding connections has a plurality of second bonding feet, wherein these are arranged on the connection surface of the power semiconductor.
  • each bonding connection has at least one end on the connection surface, preferably one end is provided on the load potential surface and one end is provided on the connection surface, more preferably the bond connection ends at its ends in each case by means of a bonding foot.
  • the plurality of bond connections are arranged in at least two groups of a plurality of bond connections of the same number of bond feet.
  • the second bond feet of each bond connection of a group are arranged exclusively in a segment or area of the connection area defined by a partial area of the connection area.
  • the segments or the regions of the different groups are arranged spatially separated from each other or expressed with respect to the second bond feet: according to the invention, there is no spatially overlapping arrangement of the second bond feet of the groups.
  • the second bond feet of each bond connection of a group are preferably arranged exclusively in exactly one common partial area of the connection area.
  • the partial surface is preferably closed in itself. Preferably, 15 to 50 bonds, more preferably 16 to 30 bonds, are provided per group.
  • the groups differ from one another in that their first bond feet are arranged on the load potential area in a different, but preferably within each group, matching distance to the power semiconductor.
  • further bonding connections can be provided. These are provided, for example, to electrically connect the control potential surfaces with the associated control pads of the controlled power semiconductor.
  • the basic idea of the invention is to make the current density more homogeneous on the connection pad of the power semiconductor which conducts the load current in comparison to the prior art. It has been shown that a particularly uniform load current distribution and thus distribution of the ohmic heat losses via the bonding connections is achieved by the embodiment according to the invention, in which the current supply or discharge per group is limited to a region of the pad of the power semiconductor.
  • the inventively further developed bond from a load potential surface to a contact surface, or metallization of the power semiconductor device has a plurality of individual bonding wires, or bonding tapes, which in turn a plurality of have second bond feet on the metallization of the power semiconductor device.
  • These second bond feet can be arranged arbitrarily.
  • a regular arrangement of the second feet in the relevant segment or area is preferred.
  • the arrangement of the second, belonging to a group group feet is checkerboard, the second bond feet are here only on fields of the same "color" so arranged offset from row to row.
  • Preferred is an arrangement in parallel, equal rows, maintaining the distances between the next adjacent second feet in the two directions.
  • the bond connections are preferably arc-shaped between the bonding feet in order to mechanically stress the bond feet as little as possible on tension and / or pressure given a temperature-induced expansion of the bond connection.
  • the bond connections of a group do not differ in length. More preferably, the bond compounds of the groups all have the same length.
  • the material of the bonds associated with the groups aluminum or copper.
  • the bond is made of high purity aluminum or high purity copper, with a purity of 99.99% or better.
  • the bonds may consist, for example, of an aluminum or copper alloy, with additives such as magnesium, silicon, silver or the like, for example the thermal or the electrically conductive properties or the mechanical properties of the bond compounds, additives being provided as alloying addition.
  • the bonding connections are preferably bonding wires.
  • the bonding wires have a round cross-section.
  • the cross-sectional diameter is in the range of 100 ⁇ to 800 ⁇ , more preferably in the range of 125 ⁇ to 500 ⁇ , such as 300 ⁇ .
  • the bond connections of a group each have a third bond foot, which is arranged in the course of the bonding connection between the first and the second bond feet and on a isolated to the load potential surface metallization of the substrate.
  • An insulated arrangement in the sense of the invention relates to the metallization per se and is thus not inconsistent with the electrical connection produced by the bond connection.
  • the metallization is electrically connected to the load potential area exclusively via at least one bonding connection. by virtue of the additional sheet guide resulting from the additional bond foot results in an extension of the relevant bond connections. This provides the ability to match the different groups with respect to the length of their bonds.
  • the additional bonding foot provides additional mechanical stabilization of the bond connection, without negatively influencing the current distribution in the sense of the basic idea of the invention due to the arrangement on the isolated metallization.
  • the third bond feet of the group are preferably arranged on a common metallization of the substrate, as a result of the connection with the substrate, among other things, an advantageous cooling. For example, they are arranged along an imaginary line running parallel to and spaced from one edge of the power semiconductor.
  • segments in the sense of the invention means regions which are arranged electrically insulated from one another, for example metallizations whose electrical insulation results from the arrangement on the substrate, but an electrical connection is not excluded
  • the connection is made via the load connection part, thereby effecting the common load current supply to and from the segments, for example, the segments are arranged parallel spaced from the opposite edges of the power semiconductor electrical and mechanical connection with external conductor ends and possibly the lead out of the electrical connection from a housing of the power semiconductor module is formed, for example, as a mirror-symmetrical trained bracket.
  • the power semiconductor module according to the invention consequently comprises at least one connection part, which is designed as a symmetrical bracket and whose strap ends are in touch contact, preferably solder contact, with the two segments of the load potential surface.
  • the bracket is a metal molding, preferably a metal molding of copper or a copper alloy.
  • the bond connections of the groups are arranged such that a mirror symmetry results with respect to their arrangement.
  • bonds which are not subject to this symmetry for example those which serve to connect the control terminals of the power semiconductor to associated control potential areas.
  • at least two groups differ in the number of second bond feet per bond connection. For example, one group has two second bond feet per bond connection, while another group has three second bond feet per bond connection.
  • the group with the largest distance to be bridged by the associated bonding connections between the associated load potential area or associated load potential area segment and associated contact area area or contact area segment has the lowest number of second bond feet per bond connection.
  • the power semiconductor has a minimum edge length in the range of 8.0 mm to 50.0 mm, preferably in the range of 9.0 to 25.0 mm, more preferably in the range of 10.0 mm to 20.0 mm ,
  • the power semiconductor module further comprises a housing, for example a housing made of plastic, preferably made of a fiber-reinforced plastic, such as a fiber-reinforced thermoplastic.
  • the housing is designed as Stülpgephaseuse.
  • the power semiconductor module according to the invention comprises exactly two power semiconductors or a number of power semiconductors which corresponds to the multiple of two.
  • a number of substrates corresponding to the number of power semiconductors is provided.
  • the bond connections of the first power semiconductor are arranged in two groups of a plurality of bond connections of the same number of bond feet and the second bond feet of each bond connection of a group are arranged exclusively in a segment or area of the connection area defined by a partial area of the connection area.
  • the groups of the first semiconductor differ in that their first bond legs are disposed on another segment of two segments of the load potential area of the first power semiconductor, which are respectively disposed adjacent two diametrically opposite edges of the first power semiconductor.
  • the exactly one load potential area of the second power semiconductor connected to the bond connections of the second power semiconductor is arranged between the first and second power semiconductors adjacent to an edge of the second power semiconductor and one of the remaining edges of the first power semiconductor.
  • the load potential area of the second power semiconductor is formed by a metallization of the substrate, which is simultaneously in touch contact with the first power semiconductor and / or one of the second Power semiconductor associated additional load potential area forms.
  • the power semiconductors are selected from the group comprising bipolar transistor, thyristor, diode. Exactly two power semiconductors are preferably a pairing of different power semiconductors.
  • the invention further relates to an arrangement of a heat sink and a power semiconductor module in one of the previously described embodiments and with the corresponding aforementioned technical advantages.
  • Figure 1 is a plan view of a first embodiment of the power semiconductor module 10 according to the invention.
  • FIG. 2 shows a detailed view of the power semiconductor module from FIG. 1;
  • FIG. 3 shows a further detailed view of the power semiconductor module from FIG. 1;
  • FIG. 4 shows a plan view of a second embodiment of the power semiconductor module 10 according to the invention.
  • FIG. 5 shows a plan view according to FIG. 4 with the removal of some components to clarify the structure shown in FIG. 4;
  • FIG. 6 shows a plan view according to FIG. 4 with the removal of other components for clarification of the construction shown in FIG.
  • FIGS. 1 to 3 show a first embodiment of the power semiconductor module 10 according to the invention
  • FIGS. 4 to 6 show a second embodiment of the power semiconductor module 10 according to the invention.
  • the modules of the first and second embodiments differ essentially by the power semiconductors 1, 2 used and by details of the bonding connection structure, in particular that of the second power semiconductor 2.
  • the first embodiment according to FIGS. 1 to 3 has two thyristors as first power semiconductor 1 and second power semiconductor 2
  • the embodiment of FIGS. 4 to 6 has two diodes as first power semiconductor 1 and second power semiconductor 2, respectively.
  • the power semiconductor module 10 of the first embodiment has a metallic base plate 5, which serves the arrangement and mounting on a heat sink, not shown.
  • a metallic base plate 5 which serves the arrangement and mounting on a heat sink, not shown.
  • two electrically insulating substrates 3, 4 are applied from ceramic.
  • a plurality of metallizations are respectively applied to the surface of the substrate 3, 4 facing away from the base plate 5, one each serves to attach and electrically contact a main surface of the power semiconductor 1, 2 arranged thereon.
  • Other metallizations of the substrates 3, 4 serve to provide load potential surfaces 13a, 13b, 23 for the power semiconductors 1, 2.
  • the first power semiconductor 1 is assigned, among other things, the load potential area formed by the two segments 13a, 13b.
  • a plurality of bond connections 15, 16 made of aluminum bonding wires or alternatively copper bonding wires are provided, which are arranged substantially parallel to one another.
  • Each of these bond connections 15, 16 has a first bonding foot 31, which is characterized in that it has a contact contact with a load potential surface or an associated segment.
  • Each of these bonding connections 15, 16 has at least two, here three second, bonding feet 32, which are characterized in that they are arranged on a connection surface 11 or an associated region or as here a segment 12a, 12b of the connection surface 11. All of the subsequently described bond feet 31, 32, 33 are connected by US wedge-wedges with the metallization touched by the bond. The segments 12a and 12b are also due to the functional wiring of the power semiconductor 1 to a pad 1 1 here the cathode pad summarized. The description of each first 31 and second 32 Bondfußes in the figures has been omitted for the sake of clarity. Between the bond feet 31, 32, the bonds form bows, which are shown more clearly in FIG. 3 with respect to the bond connections of the first power semiconductor 1.
  • the bond connections of the groups 15 and 16 are characterized in that they all have the same number of second bond feet 32 and have an end lying on the contact surface 11. Accordingly, a non-illustrated bond that extends from a load potential surface segment 13a to form a plurality of second bond legs 32 on the land 1 1 but without terminating thereon and to the other load potential surface segment 13b would also end up not as an inventive and thus considered to one of the groups associated bond.
  • the differentiation and division of the bond connections 15 and 16 into groups results, on the one hand, from the fact that the bond connections of a group are arranged exclusively in a segment defined by a partial surface of the connection surface, namely 12a or 12b of the connection surface 11 and, on the other hand, in that the first Bonded feet 31 are arranged on another segment 13a and 13b of the load potential surface. It has been found that the invention parallel and ramifying current supply and discharge and in the best case as here extending to the segments of the pad extending branching has an advantageous effect on the power distribution, in particular compared to a previously known, about the plurality of segments of the pad extending bond connection.
  • the arrangement of the second bond feet 32 of the bond connections of the power semiconductor 1 have a mirror symmetry along an axis 44.
  • the embodiment according to the invention particularly relates to the second power semiconductor 2, which is arranged on the further substrate 4.
  • the specific embodiment of the bonding connections 25, 26 can be seen in detail in FIG. It is in the power semiconductor 2 is also a thyristor.
  • the plurality of bond connections 25, 26 are arranged in at least two groups 25 and 26 of a plurality of bond connections of the same number of bond feet 31 and 32 and the second bond feet 32 of each bond connection of a group exclusively in one by a self-contained, common partial surface of the connection surface defined segment 22a and 22b of the pad 21 are arranged.
  • the groups differ in that their first bond feet 31 are arranged in a different, but within each group, matching distance ai or a 2 to the power semiconductor (2) on the associated load potential area 23 located here on the substrate 3.
  • the distance a2 of that group 26, whose associated segment 22a is arranged spatially closer to the relevant load potential area 23, is chosen to be greater than the distance a1 of that group 25 whose associated segment 22b is arranged spatially farther away to the respective load potential surface, resulting in at least approximately a match in the length of the bonds 25, 26 results.
  • the power semiconductor module 10 of the second embodiment shown in FIGS. 4 to 6 has a metallic base plate 5, which serves for the arrangement and mounting on a heat sink (not shown). On the side facing away from the heat sink of the base plate 5, two electrically insulating substrates 3, 4 are applied from ceramic. On the base plate 5 facing away from the surface of the substrate 3, 4 each have a plurality of metallizations are applied, each one serves the attachment and electrical contacting of a major surface of the power semiconductor 1, 2 arranged thereon, each of which is a power diode as mentioned above. Other metallizations of the substrates 3, 4 serve to provide load potential areas 13a, 13b, 23 for the power semiconductors 1, 2.
  • the power semiconductor 1 is assigned, inter alia, the load potential area formed by the two segments 13a, 13b.
  • the assignment of the segments 13a, 13b to a load potential area results from the same functional wiring of the power semiconductor, in this case the anode terminal of the power semiconductor 1, but also correspondingly by the parallel current supply or removal of a connection part, not shown, which is bow-shaped and mirror-symmetrical is and the legihableiter 1 is arranged across and is soldered with its free bracket ends on the load potential surfaces 13a, 13b seated with this.
  • Each of these bond connections 15, 16 has a first bonding foot 31, which is characterized in that it has a contact contact with a load potential surface or an associated segment 13a or 13b.
  • Each of these bonding connections 15, 16 has at least two, here three second, bonding feet 32, which are characterized in that they are arranged on a connection surface 11 or an associated region 12a, 12b of the connection surface 11.
  • the areas 12a and 12b are here distinguished from each other by dotted lines, a segmentation is not present but the pad 1 1 is defined in contrast to that of the power semiconductor 1 of the first embodiment by a continuous metallization.
  • the description of each first 31 and second 32 Bondfußes in the figures has been omitted for the sake of clarity. Between the bond feet 31, 32, the bonds form bows.
  • the bond connections of the groups 15 and 16 are characterized in that they all have the same number of second bond feet 32 and have an end lying on the contact surface 11.
  • the differentiation and division of the bonds 15 and 16 in groups results on the one hand in that the Bond connections of a group exclusively in a defined by a partial surface of the pad area, namely 12a and 12b of the pad 1 1 are arranged and on the other hand in that their first bond feet 31 are arranged on another segment 13a and 13b of the load potential surface. It has been found that the invention parallel and ramifying current supply and discharge and in the best case as here extending to the segments of the pad extending branching has an advantageous effect on the power distribution, in particular compared to a previously known, about the plurality of segments of the pad extending bond connection.
  • the inventive design of the bond relates in particular to the second power semiconductor 2 which is arranged on the further substrate 4.
  • the specific embodiment of the bonding connections 25, 26 can be seen in detail in FIG. 5 and illustrated here by the bonding connections 25 and 26 shown by way of example. It is in the power semiconductor 2 is also a diode.
  • the plurality of bond connections 25, 26 are arranged in at least two groups 25 and 26 of a plurality of bond connections of the same number of bond feet 31 and 32, and the second bond feet 32 of each bond connection of a group exclusively in one by a common self-contained partial surface of the pad defined region 22a and 22b of the pad 21 is arranged.
  • FIG. 1 As should be clarified in FIG.
  • the groups differ in the number of bond feet. While the group 25 has a total of 3 bond feet and only two second bond feet 32 thereof, the group 26 has a total of 5 bond feet and of which 3 second bond feet.
  • a third bonding foot 33 is provided in each case between the second bonding feet 32 located on the connection surface 21 and the first bonding foot 31 located on the load potential surface 23, said metallization being arranged on a metallization which is electrically insulated on the substrate 4 for the load potential surface 23 and the connection surface 21 30 is arranged. Only one group 26 has third bond feet 33 in their bonds, all of which are arranged on a closed surface of the metallization 30.
  • the bond connections of the two groups also differ in that their first bond feet 31 are arranged at a different distance ai and / or a 2 to the power semiconductor 2 matching within each group on the associated load potential area 23 located here on the substrate 3.
  • the distance a2 of that group 26, whose associated segment 22a is arranged spatially closer to the relevant load potential area 23, is chosen to be greater than the distance a1 of that group 25 whose associated segment 22b is spatially farther away from the relevant one Load potential surface is arranged, which results in at least approximately a match in the length of the bonds 25, 26 in cooperation with the feature of the differing number of second bond feet 32 and the additional third Bondfuß 33.
  • the load potential area 23 is defined by a metallization, which extends below the first power semiconductor 1, contacting it on its main surface facing the substrate 3, to the other side, in order to define a connection area 14 and soldering area for a connection part (not shown) ,

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Power Conversion In General (AREA)

Abstract

L'invention concerne un module de semi-conducteur de puissance (10) comprenant : au moins un substrat (4); au moins un semi-conducteur de puissance (2), disposé sur le substrat (4), qui possède sur son côté opposé au substrat une surface de connexion (21); une surface de potentiel de charge (23), éventuellement segmentée, disposée sur le substrat (4) à côté du semi-conducteur de puissance (2); et une pluralité de connexions de soudage (25, 26) destinée à relier électriquement en parallèle la surface de connexion (21) à la surface de potentiel de charge (23). Chaque connexion de soudage (25, 26) comporte au moins une première patte de soudage (31) sur la surface de potentiel de charge (23) et une pluralité de deuxièmes pattes de soudage (32) sur la surface de connexion (21) et chaque connexion de soudage (25, 26) comporte sur la surface de connexion (21) au moins une extrémité. La pluralité de connexions de soudage (25, 26) sont agencées en au moins deux groupes (25 ou 26) constitués d'une pluralité de connexions de soudage d'un même nombre de pattes de soudage et les deuxièmes pattes de soudage (32) de chaque connexion de soudage d'un groupe sont disposées exclusivement dans un segment ou zone (22a ou 22b) de la surface de connexion (21) défini par une partie de la surface de connexion et les groupes diffèrent en ce que leurs premières pattes de soudage (31) sont disposées à une distance (a1 ou a2), différente mais de préférence en coïncidence dans chaque groupe, par rapport au semi-conducteur de puissance (2) sur la surface de potentiel de charge (23).
EP16708666.9A 2015-03-12 2016-03-08 Module de semi-conducteur de puissance pourvu d'une structure de connexion par soudage améliorée Pending EP3268989A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015103667.3A DE102015103667A1 (de) 2015-03-12 2015-03-12 Leistungshalbleitermodul mit verbesserter Bondverbindungstruktur
PCT/EP2016/054894 WO2016142372A1 (fr) 2015-03-12 2016-03-08 Module de semi-conducteur de puissance pourvu d'une structure de connexion par soudage améliorée

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EP3268989A1 true EP3268989A1 (fr) 2018-01-17

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EP (1) EP3268989A1 (fr)
JP (1) JP6479207B2 (fr)
CN (1) CN107210281B (fr)
DE (1) DE102015103667A1 (fr)
RU (1) RU2676190C1 (fr)
WO (1) WO2016142372A1 (fr)

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CN116130469A (zh) * 2023-04-19 2023-05-16 烟台台芯电子科技有限公司 一种功率半导体器件
DE102024204484A1 (de) * 2024-05-15 2025-11-20 Siemens Aktiengesellschaft Elektronikanordnung

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US6054765A (en) * 1998-04-27 2000-04-25 Delco Electronics Corporation Parallel dual switch module
EP1764832A1 (fr) * 2005-08-24 2007-03-21 Semikron Elektronik GmbH & Co. KG Patentabteilung Connexion de fixation pour des composants semiconducteurs de puissance
EP2802007A1 (fr) * 2013-05-08 2014-11-12 ABB Technology AG Module de puissance à semi-conducteur

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JP6479207B2 (ja) 2019-03-06
CN107210281A (zh) 2017-09-26
CN107210281B (zh) 2020-01-31
RU2676190C1 (ru) 2018-12-26
JP2018508126A (ja) 2018-03-22
DE102015103667A1 (de) 2016-09-15
WO2016142372A1 (fr) 2016-09-15

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