EP3446328A1 - Dispositif photorécepteur multicouche, à paramètres de maille différents - Google Patents
Dispositif photorécepteur multicouche, à paramètres de maille différentsInfo
- Publication number
- EP3446328A1 EP3446328A1 EP17716935.6A EP17716935A EP3446328A1 EP 3446328 A1 EP3446328 A1 EP 3446328A1 EP 17716935 A EP17716935 A EP 17716935A EP 3446328 A1 EP3446328 A1 EP 3446328A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- openings
- interface layer
- deposited
- grains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
- H10F10/142—Photovoltaic cells having only PN homojunction potential barriers comprising multiple PN homojunctions, e.g. tandem cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
- H10F10/161—Photovoltaic cells having only PN heterojunction potential barriers comprising multiple PN heterojunctions, e.g. tandem cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/17—Photovoltaic cells having only PIN junction potential barriers
- H10F10/172—Photovoltaic cells having only PIN junction potential barriers comprising multiple PIN junctions, e.g. tandem cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/12—Active materials
- H10F77/124—Active materials comprising only Group III-V materials, e.g. GaAs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/30—Coatings
- H10F77/306—Coatings for devices having potential barriers
- H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
- H10P14/274—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using seed materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2926—Crystal orientations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3421—Arsenides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- Multilayer photoreceptor device with different mesh parameters Multilayer photoreceptor device with different mesh parameters
- photoreceptor device is understood here to mean any electronic device capable of converting a light reception, either into electrical energy such as photovoltaic devices, or into an electrical signal, such as photoresistances.
- At least two materials may be involved in the manufacture of such a device. This is for example:
- GaAs gallium arsenide
- AlGaAs binary material
- a difficulty of depositing such a material on the other consists in that their respective crystallographic structures have different mesh parameters (different interatomic distances of the material Si, to the other GaAs).
- the surface of the thin layer (intended to receive the light) is textured to trap the light, and hence to increase the photon-material interaction surfaces of the photoreceptor device.
- texturing the surface of a thin layer after its growth is delicate and time consuming to achieve performance remaining suboptimal.
- the present invention improves this situation.
- a photoreceptor device comprising at least:
- a first crystalline semiconductor material comprising a first mesh parameter
- a second semiconductor crystalline material deposited on the first material and comprising a second mesh parameter, different from the first mesh parameter.
- the device comprises an interface layer between the first and the second material, made of an amorphous material and structured to include regularly spaced openings in the plane of the layer,
- the second material comprises protuberances emerging from the openings of the interface layer and forming disjoint crystal grains, each grain having a plurality of facets forming at least one angle between them.
- the interface layer is made of an insulating material (for example an oxide, such as silica deposited on silicon as the first material). Nevertheless, the thickness of the interface layer is less than 10 nm (nanometers) to advantageously form a tunnel junction between the first and the second material. With such a small interface layer thickness, however, the formation of the aforementioned crystalline protuberances without dislocation was found.
- an insulating material for example an oxide, such as silica deposited on silicon as the first material.
- the openings of the interface layer may, for their part, have a width of, for example, between 10 and 100 nm, preferably of the order of 50 nm.
- the first crystalline material is preferably of [111] orientation, which makes it possible, as will be seen in more detail below, to avoid twin problems between regions of different crystalline orientations, when the second material is polar (such as gallium arsenide).
- the photoconductive device includes a tandem cell and the first material is used in a first "bottom” cell (bottom cell with respect to the incidence of light), while the second material is used in a first cell.
- second "top” cell top cell
- the spaces between the crystalline grains obtained can then be filled by an insulating layer deposited on the second material (for example silica S102 as illustrated with reference to step S16 of FIG. 5).
- an insulating layer deposited on the second material for example silica S102 as illustrated with reference to step S16 of FIG. 5.
- This insulating layer and the grains may then be encapsulated in a conductive and transparent layer (for example of ⁇ as shown in FIG. 5), deposited on the insulating layer (Si0 2 ).
- a conductive and transparent layer for example of ⁇ as shown in FIG. 5
- the present invention also relates to a method for manufacturing a photoreceptor device of the above type, the method comprising in particular at least:
- a first step of forming the aforementioned interface layer structured to present regularly spaced openings and opening onto the first material
- the method may further comprise an intermediate step, between said first and second stages, of depositing a seed of a third material in each of the openings, seed on which is deposited, during said second step, the second material. This seed may be of the same material as the second material, or not.
- the deposition steps are preferably carried out by epitaxy.
- the method may comprise a prior step of arranging the regularly spaced openings in the interface layer, by applying a mask etched locally to form these openings. Such an embodiment will be described in detail with reference to FIG. 5, hereinafter.
- this mask is partially etched to leave, at the openings, an interface layer thickness thinner than outside the openings (this thickness being 0.6 nm in an embodiment shown below).
- This thinner layer thickness makes it possible to avoid oxidation, in the open air, of the first underlying material. It is then removed before operating the second step or the intermediate step mentioned above.
- FIG. 1 illustrates an example of growth-related dislocations. from one material to another, in disagreement with mesh
- FIG. 2 schematically shows the structure for depositing a thin layer 10 (formed of a multiplicity of protuberances), with mesh clash, on a substrate 11, and this via a regularly “perforated” interface layer 12,
- FIGS. 3a and 3b are transmission electron microscopy images of a protuberance of gallium arsenide, deposited on a silicon substrate oriented [001] through a silica interface layer, at an epitaxial deposition temperature (CBE for "Chemical Beam Epitaxy") of 575 ° C ( Figure 3a) and 550 ° C ( Figure 3b),
- CBE epitaxial deposition temperature
- FIG. 4 is a microscopy image representing, on a scale, a protuberance, the interface layer, and the substrate
- FIG. 5 illustrates the different steps of an exemplary method of manufacturing the aforementioned interface layer
- FIG. 6 is a microscopy image showing several regularly spaced protuberances, obtained by the implementation of the method of FIG. 5, on a Si substrate of crystalline orientation [111].
- gallium arsenide 10 is deposited by epitaxy on a silicon substrate 11 (or on a preparation layer, based on silicon). However, there is provided an interface layer 12 made of oxide (silica Si0 2 in the example described) between the substrate 11 and the deposited material 10. The thickness e of the interface layer is less than order of 2 nm (nanometers). This layer 12 of oxide is "perforated” in regular places to expose the substrate 11 to bare, in openings of diameter L of the order of 20 to 100 nm. The gallium arsenide 10 is deposited progressively on the silicon substrate 11 in the openings left by the interface layer 12.
- the deposited gallium arsenide is strongly constrained, but this stress gradually relaxes as the deposit and the gallium arsenide then forms 3D islands at the exit of the interface layer 12 (arrows of FIG. 2).
- the gallium arsenide forms a protuberance in the shape of a "mushroom" at each opening of the interface layer 12.
- Each of these protuberances 10 has facets forming angles between them, which depend on the epitaxial temperature (FIG. 3a and 3b), the crystalline orientation of the substrate, and possibly other parameters.
- these protuberances grow without dislocations.
- all these facets effectively trap the light in a photoreceptor device comprising such an overall layer 10 (formed of the various protuberances) deposited in mesh disagreement on substrate 11.
- the diameter L of the openings is relatively small (less than 100 nm) compared to the dimensions of the protuberances (of the order of a few microns in width).
- Figure 4 illustrates these respective dimensions, to scale. Nevertheless, it has been observed that the carriers could transit by tunnel effect, without difficulty between the protuberance (GaAs) and the substrate (Si), because of the fineness of the interface layer (oxide) of a few nanometers.
- the openings of the interface layer 12 must be arranged regularly in the plane of the layer 12 (in regular steps along the two axes x, y of the plane of the layer 12, the third axis z being perpendicular to the layer).
- the first step S1 consists in preparing the surface of the Si substrate, by chemical cleaning . There is a thin layer of silica Si0 2 . Then, in step S2, silicon nitride SiN is deposited on the silica layer. In the next step S3, an HSQ-type resin (for "Hydrogen silsesquioxane”) is used to re-wet the SiN surface.
- HSQ-type resin for "Hydrogen silsesquioxane
- the next step S4 consists in defining the mask by electronic lithography (definition of a chosen pattern, with regular steps in the two x, y directions of the plane of the HSQ mask).
- the resin is "developed” (removed) to leave the SiN nitride on the surface, outside of the remaining HSQ polymerized regions.
- the mask is transferred, with removal of the nitride, by RIE (for "reactive ion etching"). Then, a stack having more precisely the form illustrated in relation to the step S7 of FIG. 5, of localized SiN nitride and silica, on the Si substrate, after a post-etching cleaning, is obtained.
Landscapes
- Recrystallisation Techniques (AREA)
- Engineering & Computer Science (AREA)
- Photovoltaic Devices (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Energy (AREA)
- Semiconductor Memories (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Development (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1653419A FR3050322B1 (fr) | 2016-04-18 | 2016-04-18 | Dispositif photorecepteur multicouche, a parametres de maille differents |
| PCT/EP2017/059146 WO2017182450A1 (fr) | 2016-04-18 | 2017-04-18 | Dispositif photorécepteur multicouche, à paramètres de maille différents |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP3446328A1 true EP3446328A1 (fr) | 2019-02-27 |
Family
ID=56087429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP17716935.6A Withdrawn EP3446328A1 (fr) | 2016-04-18 | 2017-04-18 | Dispositif photorécepteur multicouche, à paramètres de maille différents |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20190115488A1 (fr) |
| EP (1) | EP3446328A1 (fr) |
| CN (1) | CN109844903A (fr) |
| FR (1) | FR3050322B1 (fr) |
| WO (1) | WO2017182450A1 (fr) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7777250B2 (en) * | 2006-03-24 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| WO2008124154A2 (fr) * | 2007-04-09 | 2008-10-16 | Amberwave Systems Corporation | Photovoltaïque sur silicium |
| US8237151B2 (en) * | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| WO2010023921A1 (fr) * | 2008-09-01 | 2010-03-04 | 学校法人上智学院 | Réseau d'éléments optiques à semi-conducteurs et procédé de fabrication associé |
| US20100236617A1 (en) * | 2009-03-20 | 2010-09-23 | Sundiode Inc. | Stacked Structure Solar Cell Having Backside Conductive Contacts |
| US9293625B2 (en) * | 2012-04-13 | 2016-03-22 | Tandem Sun Ab | Method for manufacturing a semiconductor device based on epitaxial growth |
-
2016
- 2016-04-18 FR FR1653419A patent/FR3050322B1/fr not_active Expired - Fee Related
-
2017
- 2017-04-18 US US16/094,657 patent/US20190115488A1/en not_active Abandoned
- 2017-04-18 EP EP17716935.6A patent/EP3446328A1/fr not_active Withdrawn
- 2017-04-18 CN CN201780028363.8A patent/CN109844903A/zh active Pending
- 2017-04-18 WO PCT/EP2017/059146 patent/WO2017182450A1/fr not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| FR3050322B1 (fr) | 2019-01-25 |
| WO2017182450A1 (fr) | 2017-10-26 |
| FR3050322A1 (fr) | 2017-10-20 |
| US20190115488A1 (en) | 2019-04-18 |
| CN109844903A (zh) | 2019-06-04 |
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