EP3961720A1 - Germaniumanreicherung um den kanal herum durch erhöhte blöcke - Google Patents

Germaniumanreicherung um den kanal herum durch erhöhte blöcke Download PDF

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Publication number
EP3961720A1
EP3961720A1 EP21188376.4A EP21188376A EP3961720A1 EP 3961720 A1 EP3961720 A1 EP 3961720A1 EP 21188376 A EP21188376 A EP 21188376A EP 3961720 A1 EP3961720 A1 EP 3961720A1
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EP
European Patent Office
Prior art keywords
semiconductor
zones
blocks
spacers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP21188376.4A
Other languages
English (en)
French (fr)
Other versions
EP3961720B1 (de
Inventor
Heimanu Niebojewski
Christophe PLANTIER
Shay Reboh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP3961720A1 publication Critical patent/EP3961720A1/de
Application granted granted Critical
Publication of EP3961720B1 publication Critical patent/EP3961720B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Definitions

  • said blocks are not doped when grown.
  • said semiconductor blocks remain without doping.
  • areas 25 of semiconductor material with a thickness d which can be between 3 and 5 nm or between 5 nm and 25 nm ( figure 2B ).
  • Blocks 26 of a semiconductor material based on Si 1-x Ge x are then grown by epitaxy on the semiconductor zones 25, with x > 0, x being typically provided between 20% and 60%, of preferably greater than 40%.
  • the duration of the oxidation process is provided as a function of the thickness d of the semiconductor zones, knowing that this oxidation process is preferably provided at a given temperature, for a sufficient time to allow the material of the blocks 26 and achieve maximum enrichment with the germanium contained in these blocks 26.
  • the oxidation time also depends on the germanium concentration of the blocks 26 as well as the final germanium concentration targeted at the end of the enrichment.

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP21188376.4A 2020-08-31 2021-07-29 Germaniumanreicherung um den kanal herum durch erhöhte blöcke Active EP3961720B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR2008831A FR3113766B1 (fr) 2020-08-31 2020-08-31 Enrichissement germanium autour du canal

Publications (2)

Publication Number Publication Date
EP3961720A1 true EP3961720A1 (de) 2022-03-02
EP3961720B1 EP3961720B1 (de) 2023-08-23

Family

ID=74205927

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21188376.4A Active EP3961720B1 (de) 2020-08-31 2021-07-29 Germaniumanreicherung um den kanal herum durch erhöhte blöcke

Country Status (2)

Country Link
EP (1) EP3961720B1 (de)
FR (1) FR3113766B1 (de)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080042209A1 (en) 2006-08-16 2008-02-21 Chartered Semiconductor Manufacturing Ltd. Semiconductor system using germanium condensation
US20160118251A1 (en) * 2014-10-28 2016-04-28 Globalfoundries Inc. METHODS OF FORMING DOPED EPITAXIAL SiGe MATERIAL ON SEMICONDUCTOR DEVICES
US20160247888A1 (en) * 2015-02-19 2016-08-25 International Business Machines Corporation Non-uniform gate dielectric for u-shape mosfet
EP3376545A1 (de) * 2017-03-13 2018-09-19 Commissariat à l'énergie atomique et aux énergies alternatives Transistor mit strukturierten source- und drain-bereichen, und sein bearbeitungsverfahren

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080042209A1 (en) 2006-08-16 2008-02-21 Chartered Semiconductor Manufacturing Ltd. Semiconductor system using germanium condensation
US20160118251A1 (en) * 2014-10-28 2016-04-28 Globalfoundries Inc. METHODS OF FORMING DOPED EPITAXIAL SiGe MATERIAL ON SEMICONDUCTOR DEVICES
US20160247888A1 (en) * 2015-02-19 2016-08-25 International Business Machines Corporation Non-uniform gate dielectric for u-shape mosfet
EP3376545A1 (de) * 2017-03-13 2018-09-19 Commissariat à l'énergie atomique et aux énergies alternatives Transistor mit strukturierten source- und drain-bereichen, und sein bearbeitungsverfahren

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DUTARTRE: "Facet Propagation in Si and SiGe Epitaxy or Etching", ECS TRANSACTIONS, October 2006 (2006-10-01)
MUNGI PARK ET AL: "New Graded Ge Condensation Method for Formation of Ge-on-Insulator Layer", JOURNAL OF THE KOREAN PHYSICAL SOCIETY, vol. 51, no. 3, 15 September 2007 (2007-09-15), KR, pages 1100, XP055513439, ISSN: 0374-4884, DOI: 10.3938/jkps.51.1100 *
TEZUKA ET AL.: "A novel fabrication technique of ultrathin and relaxed SiGe buffer layers with high Ge fraction for sub-100 nm strained silicon on insulator MOSFETs", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 40, 2001, pages 2866 - 2874, XP001081002, DOI: 10.1143/JJAP.40.2866
TEZUKA ET AL.: "Selectively formed high mobility SiGe on Insulator pMOSFETs with Ge-rich strained surface channels using local condensation technique", SYMPOSIUM ON VLSI TECHNOLOGY, 2004

Also Published As

Publication number Publication date
FR3113766B1 (fr) 2022-12-02
FR3113766A1 (fr) 2022-03-04
EP3961720B1 (de) 2023-08-23

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