EP4519909A1 - Module semi-conducteur comprenant au moins un premier ensemble semi-conducteur, un second ensemble semi-conducteur et un dissipateur thermique - Google Patents

Module semi-conducteur comprenant au moins un premier ensemble semi-conducteur, un second ensemble semi-conducteur et un dissipateur thermique

Info

Publication number
EP4519909A1
EP4519909A1 EP23753809.5A EP23753809A EP4519909A1 EP 4519909 A1 EP4519909 A1 EP 4519909A1 EP 23753809 A EP23753809 A EP 23753809A EP 4519909 A1 EP4519909 A1 EP 4519909A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
dielectric material
material layer
heat sink
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23753809.5A
Other languages
German (de)
English (en)
Inventor
Matthias Nährig
Jens Schmenger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP4519909A1 publication Critical patent/EP4519909A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/01—Manufacture or treatment
    • H10W40/03—Manufacture or treatment of arrangements for cooling
    • H10W40/037—Assembling together parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/40—Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Semiconductor module with at least a first semiconductor arrangement, a second semiconductor arrangement and a heat sink
  • the invention relates to a semiconductor module with at least a first semiconductor arrangement, a second semiconductor arrangement and a common heat sink.
  • the invention further relates to a power converter with at least one such power semiconductor module.
  • the invention relates to a method for producing such a semiconductor module.
  • the invention relates to a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate the behavior of such a semiconductor module.
  • a power converter is understood to mean, for example, a rectifier, an inverter, a converter or a DC-DC converter.
  • the semiconductor elements used in the semiconductor modules include transistors, diodes, triacs or thyristors.
  • the transistors are designed, for example, as insulated gate bipolar transistors (IGBTs), field effect transistors or bipolar transistors.
  • IGBTs insulated gate bipolar transistors
  • the semiconductor elements are usually contacted on a substrate.
  • the publication WO 2022/002464 A1 describes a power module with at least two power units, each of which includes at least one power semiconductor and a substrate. To ensure the required installation space for the power module To reduce and improve the all-clear signal, it is proposed that the respective at least one power semiconductor is connected, in particular cohesively, to the respective substrate, the substrates of the at least two power units each being directly cohesively connected to a surface of a common Heat sink are connected.
  • the publication US 10, 014, 238 B2 describes an electronic assembly that contains a thermal management system that may include a heat sink with electronic components mounted thereon.
  • the electronic components may be mounted on the heat sink in a staggered arrangement along a centerline substantially perpendicular to the flow direction of a coolant.
  • a semiconductor module with at least a first semiconductor arrangement, a second semiconductor arrangement and a common heat sink, the heat sink being configured so that a cooling fluid is directed in a cooling fluid flow direction, the semiconductor arrangements being arranged on a surface of the heat sink, wherein the semiconductor arrangements each have a substrate on which at least one semiconductor element is connected, in particular in a materially bonded manner, the substrates each comprising a dielectric material layer, a second dielectric material layer of the second semiconductor arrangement being different from a first dielectric material layer of the first Semiconductor arrangement differs at least in terms of its thermal conductivity, wherein the second semiconductor arrangement is arranged closest to a downstream end of the heat sink, wherein the second dielectric material layer has a higher thermal conductivity than the first dielectric material layer.
  • a power converter with at least one such semiconductor module.
  • the object is achieved according to the invention by a method for producing such a semiconductor module, in each case at least one semiconductor element, in particular in a materially bonded manner, being connected to a substrate for producing the semiconductor arrangements, with the semiconductor arrangements being connected in a further step, in particular in a materially bonded manner be connected to the surface of the heat sink.
  • a computer program product comprising commands which, when the program is executed by a computer, cause it to simulate a behavior, in particular thermal, mechanical and/or electrical, of such a semiconductor module.
  • the invention is based on the idea of improving the reliability of a semiconductor module by uniformly cooling semiconductor arrangements arranged on a surface of a common heat sink.
  • the heat is dissipated via a cooling fluid that is directed in a cooling fluid flow direction.
  • the cooling fluid can be gaseous, for example air. Additionally or alternatively, liquid cooling fluids or phase change cooling can also be used.
  • the semiconductor arrangements each have a substrate on which at least one semiconductor element is connected.
  • the semiconductor elements are, for example, connected to the respective substrate in a materially bonded manner, in particular by soldering, sintering or adhesion.
  • the substrates of the semiconductor devices each comprise a dielectric material layer for producing an electrical insulating and thermally conductive connection of the respective semiconductor elements with the common heat sink.
  • dielectric material layers can contain, among other things, a ceramic material.
  • a second dielectric material layer of the second semiconductor arrangement differs from a first dielectric material layer of the first semiconductor arrangement, at least with regard to its thermal conductivity.
  • a second dielectric material layer is used, which has a higher thermal conductivity than the first dielectric material layer. This means that uniform heat dissipation is achieved even with different levels of waste heat, which has a positive effect on the reliability of the semiconductor module and extends its service life.
  • a computer program product which includes commands which, when the program is executed by a computer, cause it to simulate a behavior of the semiconductor module, in particular thermal, mechanical and/or electrical behavior, can include a “digital twin”, also called a “digital twin”. or be trained as such.
  • a digital twin is shown, for example, in the published publication US 2017/0286572 Al. The disclosure content of US 2017/0286572 Al is incorporated by reference into the present application.
  • the “digital twin,” for example, is a digital representation of the components relevant to the operation of the semiconductor module.
  • the second semiconductor arrangement is arranged closest to a downstream end of the heat sink, with the second dielectric material layer having a higher thermal conductivity than the first dielectric material layer.
  • the common heat sink e.g. B. via a fan, supplied on one side with a cooling air flow, the cooling air flow being directed from an upstream end to a downstream end of the common heat sink becomes .
  • the second semiconductor arrangement is arranged between the first semiconductor arrangement and the downstream end of the common heat sink. Due to the thermal losses of the first semiconductor arrangement, the cooling fluid heats up when it reaches the second semiconductor arrangement.
  • the higher thermal conductivity of the second dielectric material layer results in more uniform heat dissipation and thus thermal optimization.
  • the semiconductor module has at least one third semiconductor arrangement, which is arranged between the first semiconductor arrangement and the second semiconductor arrangement, comprising a third substrate on which at least one semiconductor element is connected, in particular materially, whereby the third substrate comprises a third dielectric material layer, wherein the third dielectric material layer differs from the first dielectric material layer and/or the second dielectric material layer at least with respect to its thermal conductivity.
  • the at least three semiconductor arrangements can each include a half bridge for realizing a three-phase power converter, in particular if there are more than three semiconductor arrangements of a multilevel power converter.
  • semiconductor arrangements can be connected in parallel, which makes scaling or Modularization of the semiconductor module enables.
  • a further embodiment provides that the second dielectric material layer has a higher thermal conductivity than the first dielectric material layer and/or the third dielectric material layer. Due to the higher thermal conductivity of the second dielectric material layer, which is arranged closest to the downstream end of the heat sink, more uniform heat dissipation and thus thermal optimization is achieved.
  • the semiconductor arrangements are arranged in an offset pattern along an axis on a surface of the heat sink, with the cooling fluid flow direction extending substantially along the axis.
  • the axis can be referred to, among other things, as the flow axis, with the cooling fluid flow direction running essentially parallel to the flow axis.
  • the semiconductor arrangements are distributed alternately, in particular at variable distances, offset along the flow axis. Alternately offset here means that the semiconductor arrangements are shifted alternately to the left and right with respect to the axis. In this way, more uniform heat dissipation of the semiconductor arrangements is achieved.
  • a further embodiment provides that a substrate surface of the semiconductor arrangement arranged closest to the downstream end of the heat sink is at least 20% larger, in particular at least 50% larger, than a substrate surface of a further semiconductor arrangement arranged on the surface of the heat sink. In this way, improved heat spread can be achieved, which also results in more uniform heat dissipation, which has a positive effect on the reliability of the semiconductor module and extends its service life.
  • a further embodiment provides that a semiconductor arrangement arranged closest to the downstream end of the heat sink is configured as at least part of an inverter.
  • the semiconductor arrangement arranged at the downstream end of the heat sink has a dielectric material layer with a higher thermal conductivity.
  • inverters include switchable semiconductor elements, in particular transistors, such as IGBTs, while a rectifier, which can form a converter with an inverter, can be produced with non-switchable semiconductor elements, such as diodes. Therefore, an inverter of this type can occur during operation.
  • a larger temperature swing occurs when current flows, with a higher thermal conductivity of the dielectric material layer significantly reducing the temperature swing, which has a positive effect on the service life of the semiconductor module.
  • a further embodiment provides that the substrates of the semiconductor arrangements are each directly and materially connected to the surface of the common heat sink via a connecting layer.
  • a direct cohesive connection is to be understood as a direct connection that includes connecting means for producing the cohesive connection such as adhesive, a soldering alloy, sintering paste, ..., an additional connecting element such as an additional conductor, a bonding wire, a spacer, etc.
  • base plate, thermal paste, etc. are excluded.
  • a further embodiment provides that at least the first dielectric material layer of the first substrate contains aluminum oxide and at least the second dielectric material layer of the second substrate contains aluminum nitride. While aluminum oxide is more cost-effective, aluminum nitride makes a smaller contribution to the temperature swing, so that the overall temperature swing is reduced. For example, aluminum oxide contributes 40 K to the temperature swing, while aluminum nitride only contributes 36 K. By using the more expensive aluminum nitride in the semiconductor arrangement arranged at the downstream end of the heat sink, more uniform heat dissipation is achieved and thus the service life of the semiconductor module is improved.
  • a further embodiment provides that a first connecting layer for connecting the first substrate is thinner than a second connecting layer for connecting the second substrate.
  • the second connection layer is 1.2 times thicker than the first connection layer.
  • the expansion coefficient of aluminum nitride differs more from that of a metallic surface of the heat sink, which e.g. B. Contains copper or aluminum, as the expansion coefficient of aluminum oxide.
  • a thicker connecting layer absorbs more stress due to unequal expansion coefficients and therefore has a stronger stress buffering effect between the respective dielectric material layer and the metallic heat sink.
  • a thicker second connecting layer therefore prevents the heat sink from bending due to unequal expansion coefficients.
  • a further embodiment provides that a first connecting layer for connecting the first substrate is made of a first alloy and a second connecting layer for connecting the second substrate is made of a second alloy, the first alloy differing from the second alloy in terms of its composition .
  • the second connecting layer for connecting the second substrate is exposed to a higher thermal load, so that a cheaper and less performant alloy is sufficient for the first connecting layer for connecting the first substrate.
  • a further embodiment provides that the second alloy has a higher mass fraction of antimony than the first alloy.
  • a cheap SAG (tin/silver/copper) solder is used for the first alloy, while a more performant tin-antimony alloy is used for the second alloy to connect the second substrate, which is exposed to a higher thermal load. An improved cost position is thus achieved with a high level of reliability of the semiconductor module.
  • a further embodiment provides that the substrates of the semiconductor arrangements each have a thickness of 25 pm to 400 pm, in particular 50 pm to 250 pm. Such a thickness represents a compromise in terms of thermal optimization and deflection of the heat sink.
  • FIG. 1 shows a schematic perspective view of a first embodiment of a semiconductor module
  • FIG. 2 shows a schematic cross-sectional representation of a second embodiment of a semiconductor module
  • FIG. 3 shows a schematic cross-sectional representation of a third embodiment of a semiconductor module
  • FIG. 4 shows a schematic representation of a fourth embodiment of a semiconductor module in a top view
  • FIG. 5 shows a schematic representation of a power converter with a semiconductor module.
  • the described components of the embodiments each represent individual features of the invention that can be viewed independently of one another, which each also develop the invention independently of one another and thus also individually or in a combination other than that shown as part of the invention are to be viewed. Furthermore, the embodiments described can also be supplemented by further features of the invention that have already been described.
  • the same reference numbers have the same meaning in the different figures.
  • FIG. 1 shows a schematic perspective view of a first embodiment of a semiconductor module 2, which comprises a first semiconductor arrangement 4, a second semiconductor arrangement 6, a third semiconductor arrangement 8, the semiconductor arrangements 4, 6, 8 being in an offset pattern along an axis 10 a surface 12 of a common heat sink 14 are mounted.
  • the common heat sink 14 is configured by cooling fins 16, which are designed as cooling fins, so that a gaseous cooling fluid flows in a coolant flow direction 18 along the cooling fins, the cooling fluid flow direction 18 extending substantially parallel to the axis 10.
  • the semiconductor module 2 is therefore cooled on one side.
  • the second semiconductor arrangement 6 is arranged closest to a downstream end 20 of the common heat sink 14.
  • the semiconductor arrangements 4, 6, 8 each include a substrate 22, 24, 26, on which semiconductor elements 28 are connected, in particular materially.
  • the semiconductor elements 28 are designed as transistors T and diodes D connected in opposite parallel.
  • the transistors T are designed as vertical power transistors, for example as insulated gate bipolar transistors (IGBTs).
  • IGBTs insulated gate bipolar transistors
  • the substrates 22, 24, 26 each comprise a dielectric material layer 30, 32, 34, in particular metallized on both sides, via which the respective semiconductor elements 28 are connected to the common heat sink 14 in an electrically insulating and thermally conductive manner.
  • a second dielectric material layer 32 of the second semiconductor arrangement 6 differs at least from a first dielectric material layer 32 of the second semiconductor arrangement 6.
  • a third dielectric material layer 34 of the third semiconductor arrangement 8 can differ from the first dielectric material layer 30 and/or the second dielectric material layer 6 in terms of its thermal conductivity.
  • the cooling fluid flowing in the coolant flow direction 18 can heat up due to the heat loss generated in the semiconductor elements 28 of the first semiconductor arrangement 4 and third semiconductor arrangement 8, so that a higher thermal conductivity of the second dielectric material layer 32 results in more uniform cooling of the semiconductor arrangements 4, 6, 8 leads .
  • the first dielectric material layer 30 of the first substrate 22 and the third dielectric material layer 34 of the third substrate 26 are made of aluminum oxide
  • the second dielectric material layer 32 of the second substrate 24 closest to the downstream end 20 of the common heat sink 14 is made of aluminum nitride which has a higher thermal conductivity than aluminum oxide. In this way, temperature swings during operation of the semiconductor module 2, for example in the area of the second semiconductor arrangement 4, are reduced, which has a positive effect on the service life of the semiconductor module 2.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)

Abstract

L'invention concerne un module semi-conducteur (2) comprenant au moins un premier ensemble semi-conducteur (4), un second ensemble semi-conducteur (6) et un dissipateur thermique commun (14), le dissipateur thermique (14) étant conçu de telle sorte qu'un fluide de refroidissement est conduit dans une direction de flux de fluide de refroidissement (18) ; les ensembles semi-conducteurs (4, 6) étant placés sur une surface (12) du dissipateur thermique (14) ; les ensembles semi-conducteurs (4, 6) ayant chacun un substrat (22, 24), et au moins un élément semi-conducteur (28) étant connecté sur chacun desdits substrats, en particulier à demeure ; les substrats (22, 24) comprenant chacun une couche de matériau diélectrique (30, 32). Afin d'obtenir une fiabilité améliorée, selon l'invention, une seconde couche de matériau diélectrique (32) du second ensemble semi-conducteur (6) est différente, au moins en ce qui concerne sa conductivité thermique, d'une première couche de matériau diélectrique (30) du premier ensemble semi-conducteur (4).
EP23753809.5A 2022-08-02 2023-07-26 Module semi-conducteur comprenant au moins un premier ensemble semi-conducteur, un second ensemble semi-conducteur et un dissipateur thermique Pending EP4519909A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP22188328.3A EP4318554A1 (fr) 2022-08-02 2022-08-02 Module à semi-conducteur doté d'au moins un premier dispositif à semi-conducteur, d'un second dispositif à semi-conducteur et d'un dissipateur thermique
PCT/EP2023/070729 WO2024028186A1 (fr) 2022-08-02 2023-07-26 Module semi-conducteur comprenant au moins un premier ensemble semi-conducteur, un second ensemble semi-conducteur et un dissipateur thermique

Publications (1)

Publication Number Publication Date
EP4519909A1 true EP4519909A1 (fr) 2025-03-12

Family

ID=82786497

Family Applications (2)

Application Number Title Priority Date Filing Date
EP22188328.3A Withdrawn EP4318554A1 (fr) 2022-08-02 2022-08-02 Module à semi-conducteur doté d'au moins un premier dispositif à semi-conducteur, d'un second dispositif à semi-conducteur et d'un dissipateur thermique
EP23753809.5A Pending EP4519909A1 (fr) 2022-08-02 2023-07-26 Module semi-conducteur comprenant au moins un premier ensemble semi-conducteur, un second ensemble semi-conducteur et un dissipateur thermique

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP22188328.3A Withdrawn EP4318554A1 (fr) 2022-08-02 2022-08-02 Module à semi-conducteur doté d'au moins un premier dispositif à semi-conducteur, d'un second dispositif à semi-conducteur et d'un dissipateur thermique

Country Status (4)

Country Link
US (1) US20260052984A1 (fr)
EP (2) EP4318554A1 (fr)
CN (1) CN119547191A (fr)
WO (1) WO2024028186A1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3206717B2 (ja) * 1996-04-02 2001-09-10 富士電機株式会社 電力用半導体モジュール
DE102013223430A1 (de) * 2013-11-18 2015-05-21 BSH Hausgeräte GmbH Vorrichtung mit einem Leistungselektronikmodul zum Versorgen eines elektrischen Verbrauchers eines Haushaltsgeräts mit elektrischer Versorgungsspannung, Haushaltsgerät und Verfahren zum Herstellen einer derartigen Vorrichtung
US20170286572A1 (en) 2016-03-31 2017-10-05 General Electric Company Digital twin of twinned physical system
US10014238B2 (en) 2016-07-19 2018-07-03 Ge Energy Power Conversion Technology Ltd Method, system, and electronic assembly for thermal management
EP3933913A1 (fr) 2020-06-30 2022-01-05 Siemens Aktiengesellschaft Module de puissance pourvu d'au moins deux unités de puissance

Also Published As

Publication number Publication date
US20260052984A1 (en) 2026-02-19
CN119547191A (zh) 2025-02-28
WO2024028186A1 (fr) 2024-02-08
EP4318554A1 (fr) 2024-02-07

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