Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0421—Structural details of the set of electrodes
  • G09G2300/0426—Layout of electrodes and connections
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

• the technical field of the invention concerns an electronic chip integrating several functions and more particularly, in a particular embodiment, an electronic chip for a display.
• This solution requires managing different versions of electronic chips, which can cause supply problems, as well as clutter problems around the display.
• this solution also requires that the controller chip, the pixel line control chip and the chosen pixel column control chip be compatible with each other in terms of communication protocols, which makes this solution more complex.
• an electronic chip intended to be integrated into a display may comprise a pixel line control circuit to ensure the function of the pixel line control chip mentioned above, a pixel column control circuit to ensure the function of the pixel column control chip mentioned above and a control circuit (ensuring the function of the control chip) making it possible to control any of the pixel line control circuit and the control circuit columns of pixels within the corresponding electronic chip.
• a control circuit ensuring the function of the control chip
• connection terminals external in this case mainly output terminals, to be connected for example each to a corresponding pin of a housing for an electronic chip to be mounted for example on the display or on a logic card of the display.
• Each external connection terminal occupies a certain surface area of the electronic chip and, depending on the electronic chip, the sum of the surfaces necessary to produce the external connection terminals associated with a particular function of the electronic chip may be greater than the implantation surface area.
• the pins of its case may involve a complexity of the tracks printed on the logic card to connect said electronic chip to other components assembled on the logic card.
• the aim of the invention is to provide an electronic chip with satisfactory flexibility of use.
• the invention relates to an electronic chip comprising a first circuit associated with an electronic function and a second circuit associated with an electronic function different from the electronic function of the first circuit, the electronic chip comprising terminals of external connections, the first circuit comprising first connection terminals and the second circuit comprising second connection terminals.
• This electronic chip comprises switches each electrically connected to one of the external connection terminals, to one of the first connection terminals and to one of the second connection terminals, each switch being configured to selectively adopt:
• the electronic chip may also include one or more of the following characteristics.
• the number of external connection terminals is strictly less than the sum of the number of first connection terminals and the number of second connection terminals. This makes it possible to limit the number of external terminals when they are intended to be used to be connected to either the first circuit or the second circuit.
• the electronic chip comprises a control circuit electrically connected to the first circuit and to the second circuit, the control circuit being configured to control any of the first and second circuits.
• the electronic chip According to a characteristic of the electronic chip, it is such that: at least part of the external connection terminals are each intended to be electrically connected to a circuit for controlling a pixel of a display; the first circuit is a pixel line control circuit of the display; the second circuit is a circuit for controlling columns of pixels of the display.
• the electronic chip has the advantage of presenting two functions to allow the control of pixels respectively either in rows or in columns while limiting the number of external connection terminals.
• the electronic chip comprises means for allowing the configuration of the switches. This has the advantage of allowing an easy choice of the state of each of the switches which can then be frozen or redefined each time a device using the electronic chip is started.
• the means for allowing the configuration of the switches comprise a configuration input electrically connected to each of the switches so as to allow the propagation, from the configuration input, of a configuration signal switches. This allows the same configuration signal to simultaneously configure all the switches on the electronic chip.
• the means for enabling the configuration of the switches comprise memory cells each associated with one of the switches to enable the operation of said switch to be configured, each memory cell being configurable, preferably definitively, by a configuration function implemented in the control circuit.
• the first and second circuits are digital circuits, the first connection terminals and the second connection terminals all supporting the same low level voltage and the same high level voltage. This has the advantage that the external connection terminals, the first and second connection terminals can be dimensioned in a similar and narrow manner so as not to have to support different voltage amplitudes depending on the function chosen to be implemented among the electronic function of the first circuit and the electronic function of the second circuit.
• the electronic chip comprises a chaining output intended to be electrically connected to another electronic chip.
• the chaining output makes it possible to electrically connect several electronic chips in series to, for example, adapt to the number of rows of pixels or the number of columns of pixels of a display.
• the chaining output is constituted by one of the external connection terminals and:
• the first circuit when active, is configured to emit through one of its first connection terminals a chaining signal only after having sent a signal to each of the external connection terminals electrically connected to a corresponding line of pixels of the display;
• the second circuit when active, is configured to emit the chaining signal through one of its second connection terminals only after having sent a signal to each of the connected external connection terminals electrically to a corresponding column of pixels of the display;
• control circuit can be configured to send vertical control signals to the first circuit and to send horizontal control signals and data to be displayed to the second circuit. This is suitable for displaying images.
• the invention also relates to a display comprising a matrix of pixels and at least one electronic chip as described for controlling the display of the pixels of the matrix of pixels Px.
• the display may include several electronic chips as described
• Such a display has the advantage that it can be manufactured with a limited number of component references and that the space occupied by such components, particularly on the periphery of the pixel matrix, can be limited.
• Figure 1 schematically illustrates an electronic chip according to a particular embodiment of the present invention.
• Figure 2 schematically illustrates the electronic chip according to a particular embodiment of the present invention.
• Figure 3 schematically illustrates the electronic chip according to a particular embodiment of the present invention.
• Figure 4 schematically illustrates the electronic chip according to a particular embodiment of the present invention.
• Figure 5 schematically illustrates the electronic chip integrated in a housing.
• Figure 6 schematically illustrates a display comprising electronic chips according to the present invention for controlling pixels arranged in the form of a matrix with rows and columns.
• Figure 7 schematically illustrates a set of electronic chips chained.
• An element can for example be a connection terminal, a circuit, an input, an output or a switch as will be seen later.
• circuit associated with an electronic function it is understood that this electronic function is that to which the corresponding circuit is dedicated, this electronic function being implemented using electronic components integrated into said circuit.
• an operating environment for an electronic chip is discussed below, this environment may in particular be a logic card on which the electronic chip is plugged/connected.
• the invention relates to an electronic chip 100, embodiments of which are illustrated schematically in Figures 1 to 4.
• the electronic chip 100 comprises a first circuit 101 associated with an electronic function and a second circuit 102 associated with a different electronic function of the electronic function of the first circuit 101.
• the electronic chip 100 includes external connection terminals 103.
• the first circuit 101 comprises first connection terminals 104 and the second circuit 102 comprises second connection terminals 105.
• the electronic chip 100 comprises switches 106 each electrically connected to one of the external connection terminals 103, to one of the first connection terminals 104 and to one of the second connection terminals 105, each switch 106 being configured to selectively adopt:
• the advantage of such an electronic chip 100 lies in its flexibility of use in the sense that its operation can be configured by choosing the operating state of the switches 106, this operating state being selected in particular, for each of the switches 106, from the first state and the second state.
• a particular advantage of such an electronic chip 100 is that it makes it possible, if desired, to limit the number of external connection terminals 103 depending on the destination of use of the electronic chip 100 which can then be used to implement the electronic function of the first circuit 101 or the electronic function of the second circuit 102. Limiting the number of external connection terminals 103 of the electronic chip 100 makes it possible to limit the necessary surface area, for example on a support substrate as a silicon substrate, to form the electronic chip 100 and its external connection terminals 103 whatever the electronic function (for example chosen between the electronic function of the first circuit 101 and the electronic function of the second circuit 102) of the chip 100 electronic must be activated. In addition, the electronic chip 100 as described can, where appropriate, make it possible to limit the number of unused external connection terminals 103 when the electronic chip 100 is functionally connected in its operating environment.
• first and second circuits 101, 102 are both functional when using the electronic chip 100
• another particular advantage of the electronic chip 100 as described is that it allows, for example , to choose flexibly, via switches 106, which external connection terminals 103 must be electrically connected to the first circuit 101 and which external connection terminals 103 must be electrically connected to the second circuit 102 to adapt the electronic chip 100 to the operating environment in which it will be used. It can then be understood here that all the first connection terminals 104 and all the second connection terminals 105 are not necessary for the operation of the first circuit 101 and the second circuit 102 respectively.
• switch 106 is meant in the present description any system allowing, for example, to implement as desired: an electrical link between the corresponding external connection terminal 103 and the first corresponding connection terminal 104; and an electrical link between the corresponding external connection terminal 103 and the second corresponding connection terminal 105. Therefore, the switch 106 can be a switch, for example formed by a set of field effect transistors behaving like a switch controlled by a logic signal varying for example from 0 to 1 and vice versa from 1 to 0.
• each switch 106 is electrically connected to only one of the external connection terminals 103, to only one of the first connection terminals 104, and to only one of the second connection terminals 105;
• each first connection terminal 104 is electrically connected to only one of the switches 106;
• each second connection terminal 105 is electrically connected to only one of the switches 106;
• each external connection terminal 103 is electrically connected to only one of the switches 106.
• each of the external connection terminals 103 is intended to be electrically connected to an external connection member 201, also called a "pin” or “tab", of a housing 200 for housing the electronic chip 100 (this housing not being shown in Figures 1 to 4 but visible in Figure 5 in a schematic manner with the electronic chip 100 shown in dotted lines).
• the box 200 makes it possible in particular to connect the electronic chip 100 into its operating environment.
• connection members 201 of the housing 200 housing the electronic chip 100 for which all the electronic functions are not to be activated
• this also makes it possible to reduce the number of connection members 201 and therefore the bulk of the housing 200 while allowing various uses of the housing 200 in the sense that it can be used in different ways depending on the electronic function chosen within the electronic chip 100 (ie the first circuit 101 or the second circuit 102) to be connected to the external connection terminals 103.
• the external connection terminals 103 are output terminals of the electronic chip 100.
• the first circuit 101 and the second circuit 102 are each staged, that is to say they each integrate shift registers, for example. Therefore, each stage of the first circuit 101 can be connected to only one of the first connection terminals 104 of this first circuit 101 and each stage of the second circuit 102 can be connected to only one of the second connection terminals 105 of this second circuit 102. This has the advantage of scheduling the processing within the first and second circuits 101, 102 in the sense that:
• the invention also relates to a display 1000 comprising a matrix of pixels Px and at least one electronic chip 100a, 100b as described for controlling the display of the pixels Px of the matrix of pixels Px.
• the display 1000 may include several electronic chips 100a, 100b to control the display of the pixels Px of the pixel matrix Px.
• Such a display 1000 an exemplary embodiment of which is illustrated in Figure 6, has the advantage that it can be manufactured with a limited number of electronic chip references 100a, 100b and that the space occupied by such electronic chips 100a, 100b , particularly on the periphery of the matrix of pixels framed in dotted lines in Figure 6, can be limited.
• the presence of a single electronic chip 100 as described in the display 1000 it is understood that its first and second circuits 101, 102 are functional.
• the electronic chip 100 can be configured to present:
• the choice of configuration makes it possible here to limit the references of electronic chips 100 in the context of the manufacture of devices using one or more electronic chips 100, such as for example the display 1000 described above, and therefore to improve management of the 100 electronic chip supply chain.
• this choice also makes it possible to greatly limit the number of external connection terminals 103, for example by dividing it by two compared to a conventional electronic chip which would have a number of connection terminals external equal to the sum of the number of first connection terminals and the number of second connection terminals. Therefore, the electronic chip 100 makes it possible to have a reduced size and a satisfactory cost, particularly when it is of the “pad limited” type.
• the switches 106 are notably all in their first state.
• the switches 106 are notably all in their second state.
• the first circuit 101 can be considered active when at least one (or more or all) of its first connection terminals 104 is electrically connected to one of the external connection terminals 103 using one of the corresponding switches 106 in its first state.
• the first circuit 101 can be considered inactive when none of its first connection terminals 104 is electrically connected to any of the external connection terminals 103 of the electronic chip 100.
• the second circuit 102 can be considered active when at least one (or more or all) of its second connection terminals 105 is electrically connected to one of the external connection terminals 103 using one of the corresponding switches 106 in its second state.
• the second circuit 102 can be considered inactive when none of its second connection terminals 105 is electrically connected to any of the external connection terminals 103 of the electronic chip 100.
• the first circuit 101, or the second circuit 102 When the first circuit 101, or the second circuit 102, is inactive and the electronic chip 100 is in operation in the display 1000, the first circuit 101 or the second inactive circuit 102 can be turned off, i.e. not supplied with power. energy to limit the overall energy consumption of the electronic chip 100.
• this first or second active circuit 101, 102 can be supplied with energy to ensure its electronic function.
• the number of external connection terminals 103 can be such that:
• each first connection terminal 104 is electrically connected to only one of the external connection terminals 103 and none of the second connection terminals 105 is electrically connected to any of the external connection terminals 103;
• each second connection terminal 105 is electrically connected to only one of the external connection terminals 103 and none of the first connection terminals 104 is electrically connected to any of the external connection terminals 103.
• the number of external connection terminals 103 can be adapted to the design of the electronic chip 100 depending on the circuits (at least the first and second circuits 101, 102) that it integrates in order to ensure the chosen electronic function; either by choice to use the electronic chip 100 to implement the electronic function of the first circuit 101, or by choice to use the electronic chip 100 to implement the electronic function of the second circuit 102.
• all the switches 106 are in the same state as for example in the case of a display 1000 with one hundred pixel lines and a chip 100 as described comprising one hundred switches 106 implying that the one hundred switches 106 are in their first state making it possible to connect one by one, via the external connection terminals 103, the hundred lines of the display 1000 to the first hundred connection terminals 104 of the first circuit 101 which is then a “line driver” circuit , i.e. a circuit making it possible to control the pixel lines of the display 1000.
• an electronic chip 100 as described with a hundred switches 106 can be such that ninety-nine of its switches 106 allow (via their first state) to connect ninety-nine lines of pixels of the display 1000, via ninety-nine external connection terminals 103 of the chip 100, to ninety-nine first terminals 104 for connection of the first circuit 101 which is then a “line driver” circuit, and the remaining switch 106 (i.e. the hundredth) makes it possible to ensure the chaining to another electronic chip which connects other lines of pixels to be controlled from the display 1000.
• the number of external connection terminals 103 may be strictly less than the sum of the number of first connection terminals 104 and the number of second connection terminals 105. This makes it possible to limit the number of external connection terminals 103 when they are intended to be used to be connected either to the first circuit 101 or to the second circuit 102.
• the surface area of the electronic chip 100 can be limited, which is particularly advantageous when it is of the “Pad Limited” type.
• the number of external connection terminals 103 can be equal to the largest of the numbers chosen from the number of first connection terminals 104 and the number of second connection terminals 105 in order to ensure that the necessary connections can be made by the switches 106 according to their state chosen from the first state and the second state.
• N circuits including at least the first circuit 101 and the second circuit 102 formed on the electronic chip 100 and which can each be activated while the other N-l circuits remain in an inactive state; in this case, the number of external connection terminals 103 can be:
• N is a positive integer greater than or equal to 3 and the switches 106 can include N states in order to ensure, as desired, the establishment of the desired electrical links.
• the electronic chip 100 may comprise a control circuit 107, also called a controller, electrically connected to the first circuit 101 and to the second circuit 102 as shown by way of example in Figures 1 to 4.
• the circuit 107 control is configured to control any of the first and second circuits 101, 102.
• control it is here understood in particular to control the operation for example by transmitting appropriate data to be processed and, where appropriate, signals intended for timing its operation (e.g. signals conventionally used in the field of display such as a synchronization signal, a clock signal, an output activation signal, a scanning direction signal).
• the output activation signal can, for example in the case of a shift register of the corresponding circuit (if applicable the first circuit 101 or the second circuit 102), validate when data is authorized at the output of the shift register for edge synchronization reasons.
• the electronic chip 100 can also integrate a control function making it possible to control any of the first and second circuits 101, 102 for example depending on which one is ultimately active.
• the integration of a control function i.e. the control circuit 107
• this control function is necessary, of the first and second circuits 101, 102 allows the electronic chip 100 not to require an external chip to control it. .
• the electronic chip 100 may comprise a vertical signal input, a horizontal signal input and a clock signal input connected to the control circuit 107 which determines then, depending on the clock signal and one or other of the vertical and horizontal signals, within the electronic chip 100 the signals necessary for the operation, where appropriate, of the first circuit 101 or the second circuit 102
• this integration also makes it possible to simplify the electronic interfaces in the sense that the communication between the control circuit 107 and the first and second circuits 101, 102 will be directly provided within the electronic chip 100.
• control circuit 107 is integrated into the electronic chip 100 for the reasons mentioned above, it is of course possible not to do so and therefore to deport the control circuit 107 within an electronic control chip, external to the electronic chip 100, which will be electrically connected to said electronic chip 100.
• the control circuit 107 is configured to organize the operation, where appropriate, of the first circuit 101 or the second circuit 102 by providing it with electrical control and configuration signals.
• the first circuit 101 is configured to process first data in order to ensure its function and the second circuit 102 is configured to process second data in order to ensure its function, the first data and the second data being different. These first or second data can be sent to the first circuit 101 or to the corresponding second circuit 102 via the control circuit 107.
• the display 1000 also called a display panel, which can advantageously integrate several electronic chips 100.
• the pixels Px of the pixel matrix Px of the display 1000 are particularly capable of being controlled to produce a display, for example of images and in particular in the form of a video stream.
• Each Px pixel can include light-emitting diodes (not shown), such as LEDs (acronym for “Light-Emitting Diodes” in English) or OLEDs, to allow the pixel to emit at a desired wavelength.
• the pixels Px of the pixel matrix Px are ordered in columns and rows so as to form a display panel 1001 (figure 6).
• Px pixels can be controlled using one or more pixel row control circuits and one or more pixel column control circuits which are, taken independently, standard circuits well known in the art. skilled person.
• electronic chips 100 such as described to control the rows of pixels (e.g. electronic function of the first circuit 101) and the columns of pixels Px (e.g. electronic function of the second circuit 102).
• the display 1000 may comprise at least a first electronic chip 100a, and in particular first electronic chips 100a, the or each first electronic chip 100a corresponding to the electronic chip 100 as described for which the first circuit 101 is active and forms a pixel line control circuit of the display 1000, and at least one second electronic chip 100b, and in particular second electronic chips 100b, the or each second electronic chip 100b corresponding to the electronic chip 100 for which the second circuit 102 is active and forms a pixel column control circuit of the display 1000.
• first electronic chip 100a and in particular first electronic chips 100a
• the or each first electronic chip 100a corresponding to the electronic chip 100 as described for which the first circuit 101 is active and forms a pixel line control circuit of the display 1000
• at least one second electronic chip 100b, and in particular second electronic chips 100b the or each second electronic chip 100b corresponding to the electronic chip 100 for which the second circuit 102 is active and forms a pixel column control circuit of the display 1000.
• the number of first electronic chips 100a is equal to two and the number of second electronic chips 100b is equal to two; this is only illustrative in the sense that the number of electronic chips 100a, 100b within the display 1000 depends in particular on the resolution of the display 1000 in terms of the number of pixels Px and the capacities of the chips 100a, 100b electronics used in terms of the number of rows of pixels or the number of columns of pixels that they are each able to control.
• the use of several electronic chips 100 to control the rows of pixels and/or the columns of pixels can be imposed by the fact that:
• the matrix of pixels Px comprises n columns of pixels Px and p rows, with n>q where q is the number of second connection terminals 105 in the electronic chips 100 and/or with p>r where r is the number of first connection terminals 104 in electronic chips; • several electronic chips 100a with the first active circuit 101 are used if p>r;
• the electronic chip 100 can be such that: at least part of the external connection terminals 103 (i.e. all or part of the external connection terminals 103) are each intended to be electrically connected to a circuit for controlling a pixel of the display 1000; the first circuit 101 is a pixel line control circuit of the display 1000; the second circuit 102 is a pixel column control circuit of the display 1000.
• control circuit of a pixel of the display it is understood that the pixel control circuit (in particular integrated into Px in Figure 6 which also includes the pixel to be controlled) controls the emission of photons by the pixel according to the information received via an electronic chip whose first circuit 101 is active and an electronic chip whose second circuit 102 is active connected to said pixel control circuit within the display 1000 by one of the rows of pixels and one of the columns of pixels respectively to address the pixel control circuit as a function of the line of pixels which includes it and the column of pixels which includes it.
• each row of pixels of the display 1000 is connected to one of the stages of a first circuit 101 of a corresponding electronic chip 100 and each column of pixels of the display 1000 is connected to one of the stages of the second circuit 102 of a corresponding electronic chip 100.
• the first circuit 101 is connected, via all or part of the external connection terminals 103 of said electronic chip 100, to pixel lines, with an external connection terminal 103 electrically connected to only one of said pixel lines, which results in the connection of the pixel control circuits of each of said lines of pixels for example at one stage of said first circuit 101.
• the second circuit 102 is connected, via all or part of the external connection terminals 103 of said electronic chip 100, to columns of pixels, with an external connection terminal 103 electrically connected to only one of said column of pixels, from which results the connection of the pixel control circuits of each of said columns of pixels, for example to a stage of said second circuit 102.
• each pixel Px connected to these two electronic chips 100 can be addressed according to its position in the matrix of pixels given by the line of pixels to which it is connected (ie to the row of pixels which includes it) and the column of pixels to which it is connected (ie to the column of pixels which includes it).
• the first and second circuits 101, 102 allow, by being used in synergy using two electronic chips 100, one of which has its first active circuit 101 and the other has its second active circuit 102, to store digital information in pixels of the display 1000 and to control the light emission, for example of light-emitting diodes, of the pixels as a function of the values of the digital information stored in the pixels.
• such an electronic chip 100 has the advantage of presenting two electronic functions respectively to allow the control/command of pixels Px either in rows or in columns while benefiting from a reduced number of external connection terminals 103 by limiting or avoiding for example having unused external connection terminals 103 of the electronic chip 100 when one of the two electronic functions (ie the first circuit 101 or the second circuit 102) will be active while the other of the two electronic functions will be inactive.
• Electronic chips 100 can thus be manufactured so as to offer the two electronic functions of controlling lines of pixels and controlling columns of pixels, the activation of one of the electronic functions can then be done subsequently within the display 1000.
• the electronic chip 100 is used in the display 1000: either the first circuit 101 is active (as for the electronic chips 100a shown in Figure 6) and the switches 106 are then in their first state, or the second circuit 102 is active (as for the electronic chips 100b shown in Figure 6) and the switches 106 are in their second state. If the first circuit 101 is active then its first connection terminals 104 are electrically connected to all or part of the external connection terminals 103 which are each even electrically connected to a line of pixels Px of the display 1000. In particular, all the pixels of the same row of pixels of the display 1000 have at least one common electrode (i.e.
• these pixels are electrically connected to each other) for the application of a VCC potential. If the second circuit 102 is active then its second connection terminals 105 are electrically connected to all or part of the external connection terminals 103 which are each even electrically connected to a column of pixels Px of the display 1000.
• the electronic chip 100 may include a writing mode and a reading mode.
• the pixel line control circuit ie the first circuit 101, allows, in the writing mode, to control the selection of a complete pixel line of the display 1000.
• the first data can be used by the first circuit 101 to determine the line of pixels Px to select.
• the pixel column control circuit ie the second circuit 102, allows, in the writing mode, to load digital data, where appropriate from the second data, into the pixels to which the second circuit 102 is connected and belonging to a line of pixels selected by the first circuit 101 of another chip 100 electronic.
• the pixel line control circuit makes it possible, in the reading mode and for each line of pixels Px electrically connected to said pixel line control circuit, to control the emission of each pixel Px of said line of pixels and the light emission of said pixel controlled by pulse width modulation in a synchronized manner on the pixel line by the pixel line control circuit; the information necessary for controlling the emission of the pixels is contained in the first data.
• Switches 106 have been described above, the state of which, in particular chosen from the first state and the second state, makes it possible to define to which the external connection terminals 103 are electrically connected, via the electrical links. within the electronic chip 100. This being said, there is a need to make it possible to implement an easy choice of the state of each of the switches 106. To meet this need, the electronic chip 100 can include means 108 to allow the configuration of the switches 106; i.e. allow you to configure the state in which they are each chosen from the first state and the second state. Different embodiments of these means are illustrated in Figures 1 to 4.
• these means 108 for allowing the configuration of the switches 106 comprise a configuration input 109 electrically connected to each of the switches 106 so as to allow the propagation, from the configuration input 109, of a configuration signal. configuration of the switches 106.
• This embodiment is in particular that illustrated in Figures 1 and 2 and can be implemented using switches 106 formed by NMOS transistors (“Metal Oxide Semiconductor” transistors of type N for insulated gate transistors of type N ) each connected to configuration input 109 to determine the state of the corresponding switch 106.
• a switch 106 can be formed by a first NMOS transistor electrically connected to the first corresponding connection terminal 104 and to the external connection terminal 103 and a second NMOS transistor electrically connected to the second corresponding connection terminal 105 and to said external connection terminal 103.
• the first and second NMOS transistors are controlled by a signal S (corresponding to the logic signal mentioned above), the signal S propagating according to one example directly to a gate electrode of the first NMOS transistor and, according to this example, by the intermediate an inverter to a gate electrode of the second NMOS transistor so that when the first NMOS transistor is on the second NMOS transistor is blocking (ie the first connection terminal 104 is electrically connected to the external connection terminal 103 while the second connection terminal 105 is electrically isolated from the external connection terminal 103) and vice versa when the second NMOS transistor is on the first NMOS transistor is blocking (ie the second connection terminal 105 is electrically connected to the external connection terminal 103 while the first connection terminal 104 is electrically isolated from the external connection terminal 103).
• a signal S corresponding to the logic signal mentioned above
• the same configuration signal (eg the signal S) makes it possible to simultaneously configure all the switches 106 of the electronic chip 100.
• the use of the same configuration signal has the advantage that the electronic chip 100 concerned can be configured in an application external to the electronic chip 100 whereby it results that the electronic chip 100 does not need to be programmable: the propagation of the configuration signal generated by the external application and applied to the configuration input 109 within the chip 100 (in particular via wiring directly carried out within a printed circuit of the chip 100 electronic) is enough.
• the means 108 for allowing the configuration of the switches 106 can also include a track 110 connecting the configuration input 109 to the switches 106 to allow the propagation of the configuration signal.
• the means 108 for allowing the configuration of the switches 106 can comprise, as for example illustrated in Figures 3 and 4, memory cells 111, for example of 1 bit each, each associated with one of the switches 106 to make it possible to configure the operation of said switch 106 and therefore make it possible to choose the state of the latter at least from the first state and the second state .
• a programmable static or fixed memory cell is required here for each pair of stages of the first circuit 101 and the second circuit 102, the stages of which are each able to be electrically connected selectively to the same corresponding switch 106.
• Each memory cell can be configurable by a configuration function implemented in the control circuit 107, for example in configuration registers (which can be simple shift registers) of the control circuit 107 of said electronic chip 100. Furthermore, this is advantageous when the number of rows of pixels or the number of columns of pixels is not an integer multiple of the number of stages of the first circuit 101 or the second circuit 102: it can then be considered to share the operation of the electronic chip 100 so that the two electronic functions are active (i.e. that the first and second circuits 101, 102 are active), this allows optimization of the number of circuits and therefore of the cost of the display 1000.
• each memory cell by the configuration function implemented in the control circuit 107 in the following manner.
• the control circuit 107 of each electronic chip 100 will read the state that each of its switches 106 must present in an installation memory and at through a bus 117 for controlling the memory cells 111 making it possible to control the memory cells 111 (the control bus 117 making it possible to configure the switches 106 is visible in Figures 3 and 4), the control circuit 107 writes the state of each of the switches 106 in each memory cell 111.
• each memory cell 111 is configurable in a manner definitive (in this case each memory cell 111 can be of the ROM type, acronym for “read only memory” for read-only memory).
• a corresponding circuit ie the first circuit 101 or the second circuit 102 within the display 1000 is connected either to a row of pixels or to a column of pixels of the display 1000 definitively: any change electronic function causes that the display 1000 no longer functions correctly because this would amount to placing a signal for a row of pixels on a column of pixels and conversely a signal for a column of pixels on a row of pixels.
• the first and second circuits 101, 102 are preferably digital circuits, therefore the first connection terminals 104 and the second connection terminals 105 all support the same low level voltage and the same level voltage high, in particular these voltages are also supported by the external connection terminals 103.
• the first and second circuits 101, 102 are digital circuits”, it is understood that the latter are entirely digital , that is, they do not implement an analog function.
• the first and second circuits 101, 102 could also be hybrid, i.e. present digital and analog functions.
• An advantage of using digital circuits is that this makes it possible to rationalize the use of electronic chips 100 within the display 1000.
• the line control circuits of pixels and columns of analog pixels are generally different and difficult to combine within the same electronic chip, unless its internal electrical connections are oversized, because the voltages required at the external connection terminals are very different depending on the electronic function.
• the voltage on the pixel rows can be up to 45V and the voltage on the pixel columns can be up to 13V with an accuracy of 5mV in digital to analog conversion.
• the voltage on the pixel rows can be up to 25V and the voltage on the pixel columns can be up to 10V with an accuracy of 5mV in digital to analog conversion.
• Proposing circuits for controlling lines of pixels and columns of digital pixels makes it possible to benefit from an opportunity to integrate the corresponding electronic functions by using external connection terminals 103 compatible for the two electronic functions since the voltage levels will then be identical for both electronic functions.
• the pixels Px of the display 1000 are digital and, in particular, are digitally controlled in row and column.
• the display 1000 can in particular be such that it will include a set of first electronic chips 100a connected to the same first data bus 1006 and chained in series to control the pixels Px according to their line and a set of second chips 100b electronics connected to the same second data bus 1007 and chained in series to control the Px pixels according to their column. Therefore, there is a need to allow the chaining of electronic chips 100, also called cascade connection, within the display 1000.
• the electronic chip 100 can include a chaining output 112 (as illustrated for example in Figures 1 and 4) intended to be electrically connected to another electronic chip 100; this chaining output 112 makes it possible in particular to synchronize the processing of data received by the electronic chips 100 chained together (for example these data correspond to the first data received by the electronic chips 100 connected to the first data bus 1006 or to the second data received by the electronic chips 100 connected to the second data bus 1007) in the sense that the chaining output 112 makes it possible to send a chaining signal to another electronic chip 100 to indicate to it the end of the processing sequence by the electronic chip 100 which precedes it and which sent it said chaining signal in order to authorize said other electronic chip 100 to begin its own data processing sequence which it received, where appropriate, by the first data bus 1006 or by the second bus 1007 data.
• a chaining output 112 as illustrated for example in Figures 1 and 4
• this chaining output 112 makes it possible in particular to synchronize the processing of data received by the electronic chips 100 chained together (for example
• the chaining output 112 participates in forming, where appropriate, the set of first electronic chips 100a or the set of second electronic chips 100b within the framework of the display 1000 and in appropriately sequencing the processing of data to be produced by each of the electronic chips 100 (if applicable, the first electronic chips 100a or the second electronic chips 100b).
• the electronic chip 100 can include a data reception input 113 (visible in particular in Figures 1 to 4). It is to this data reception input 113 that, where appropriate, the first data bus 1006 or the second data bus 1007 is connected as part of the display 1000.
• the data presented on the input 113 receiving data during the operation of the electronic chip 100 are intended to be processed by the electronic chip 100, for example in whole or in part by the first circuit 101 or by the second circuit 102 and, where appropriate, by the control circuit 107 of the electronic chip 100.
• control circuit 107 is electrically connected to the data reception input 113 as shown in Figures 1 to 4, which then allows it, in operation, to suitably control/control the first circuit 101 or the second circuit 102 by exploiting the data received via the data reception input 113.
• its data reception input 113 is such that the data received are preferentially synchronization signals in particular to synchronize the operation of the pixels.
• its data reception input 113 is such that the data received are preferably display data to be displayed by the display 1000.
• the data reception inputs 113 of several electronic chips 100 can be connected to the same data bus (first data bus 1006 or second data bus 1007) so that the electronic chips 100 receive data which they can fully or partially process in a sequenced manner, for example using the propagation of the chaining signal sequentially to the electronic chips 100 intended to control rows of pixels or columns of pixels of the display 1000 .
• the electronic chip 100 may further comprise a chaining input 115 as for example visible in Figures 1, 4 and 7.
• This chaining input 115 can be connected to the first circuit 101 and to the second circuit 102.
• This input 115 of chaining, of the so-called current electronic chip 100 is intended to be connected, where appropriate, to the chaining output 112 of a previous electronic chip 100. In this case, as long as the previous electronic chip 100 does not emit the chaining signal, the operation of the first active circuit 101 or the second active circuit 102 of the current electronic chip 100 is inhibited to satisfy synchronization needs.
• the chaining signal can come directly from an external controller which allows you to ensure vertical or horizontal synchronization of a corresponding video.
• the external controller belongs to the display 1000 and is notably configured to clock the writing of video information (images) in the pixels of the display 1000; the images are then presented sequentially for their writing in said pixels, and the horizontal and vertical synchronization signals trigger or clock the writing of each image in said pixels, therefore define when and how the image must be written in said pixels.
• the data reception inputs 113, the chaining output(s) 112 and the chaining input(s) 115 of several electronic chips 100 make it possible to form the set of first electronic chips 100a or the set of second electronic chips 100b as part of the display 1000, the operation of which can then be sequenced in a suitable manner.
• the chaining of the electronic chips 100 makes it possible to guarantee the writing of the new image at each frame of a video to be displayed on the display 1000
• the chaining output 112 is constituted by one of the external connection terminals 103, as for example visible in Figures 1 and 4. In this particular example:
• the first circuit 101 when active, is configured to emit through one of its first connection terminals 104 the chaining signal only after having sent a signal to each of the external connection terminals 103 electrically connected to a line of connection corresponding pixels of the display 1000, this can advantageously be ensured when the first circuit 101 has a succession of stages, certain stages of which are electrically connected to the pixel lines, the last stage of the succession of stages of the first circuit 101 is then electrically connected to said one of its first connection terminals 104 and is configured to ensure the propagation of the chaining signal;
• the second circuit 102 when active, is configured to emit through one of its second connection terminals 105 the chaining signal only after having sent a signal to each of the external connection terminals 103 electrically connected to a column of corresponding pixels of the display 1000, this can advantageously be ensured when the second circuit 102 has a succession of stages, certain stages of which are electrically connected to the columns of pixels, the last stage of the succession of stages of the second circuit 102 is then electrically connected to said one of its second connection terminals 105 and is configured to ensure the propagation of the chaining signal;
• this is the first terminal 104 of the first circuit
• stages within the first circuit 101 and the second circuit 102 makes it possible to induce a temporality of data processing and to ensure that the last active stage (i.e. in the temporal sense) of the succession of stages corresponding is, depending on the case, connected to a line of pixels, a column of pixels or to the chaining output 112 to be connected to a circuit, where appropriate the first circuit 101 or the second circuit 102, of another chip 100 electronic.
• the chaining function that the first circuit 101 and/or the second circuit 102 comprises can be ensured by a shift register internal to the first circuit 101, the last stage of which is connected to the chaining output 112 via the first corresponding connection terminal 104 when the associated switch 106 is in its first state and/or by a shift register internal to the second circuit 102, the last stage of which is connected to the chaining output 112 via the second corresponding connection terminal 105 when the associated switch 106 is in its second state.
• This allows the chaining signal to be automatically transmitted to the chaining output 112 when the processing to be carried out by the first circuit 101, or the second circuit 102, is completed.
• the chaining signal sent to the chaining output 112 can also come from a last stage of a shift register, integrated into the electronic chip 100, which would control the loading of data onto associated memory registers, the where appropriate, to the rows of pixels of the display 1000 or to the columns of pixels of the display 1000.
• a set of chained electronic chips 100 What is described in connection with this set of electronic chips 100 can in particular apply indifferently to the set of first electronic chips 100a and to the set of second electronic chips 100b.
• the set of chained electronic chips comprises (see Figure 7 as an example) a primary 100e electronic chip and a final 100g electronic chip between which is/are arranged one or more intermediate electronic lOOf chips (a intermediate electronic chip 107f in the example).
• the primary electronic chip 100e, the intermediate electronic chip(s) lOOf and the last electronic chip 100g are in particular all physically identical, which makes it possible to limit the references of electronic chips 100 to be used in said set of electronic chips 100; in particular, the electronic chips 100 of the set of first electronic chips 100a and the electronic chips 100 of the set of second electronic chips 100b are also physically identical in the sense that they can be interchanged so that, for example, only the external wiring to the electronic chips 100, in particular via the external terminals 103 of the electronic chips 100, has an influence on their operation, ie the electronic chips in particular all come from the same manufacturing process.
• the primary electronic chip 100e, the intermediate electronic lOOf chip(s) and the last electronic chip 100g each receive data on their data reception input 113 (the first data or the second data as appropriate) due to the connection of these chips 100e, lOOf, 100g, via their reception input 113, to a data bus 116 (either the first data bus 1006 mentioned above or the second bus 1007 of data mentioned above) making it possible to process the pixels Px of the display 1000 either according to their row or according to their column.
• a data bus 116 either the first data bus 1006 mentioned above or the second bus 1007 of data mentioned above
• the chaining output 112 of the primary electronic chip 100e is electrically connected to the chaining input 115 of the or one of the intermediate electronic lOOf chip(s) of the set of electronic chips and thus consecutively until the chaining output 112 of one of the electronic chips (the intermediate electronic lOOf chip in the example illustrated in Figure 7) is electrically connected to the chaining input 115 of the last electronic chip 100g electronic chips of the electronic chip assembly.
• any intermediate electronic chip lOOf of the set of electronic chips and located between the primary electronic chip 100e of this set of electronic chips 100 and the last electronic chip 100g of this set of electronic chips 100 its chaining output 112 is electrically connected to the chaining input 115 of one of the electronic chips of the set of electronic chips and its chaining input 115 is electrically connected to the chaining output 112 of another of the electronic chips of the set electronic chips.
• connecting elements 114a, 114b show the chaining of the first electronic chips 100a and the second electronic chips 100b.
• control circuits 107 may have a role to play in the chaining of the electronic chips 100e, lOOf, 100g of the set of electronic chips.
• each control circuit 107 can decide when to send a chaining signal to the chaining output 112 of the electronic chip 100e, lOOf, 100g which includes it.
• it is generally the first active circuit 101 or the second active circuit 102 which activates the propagation of the chaining signal at the desired moment to ensure the synchronization of a series of electronic chips 100 chained together and connected to the same data bus 116 via their data reception input 113.
• the control circuit 107 of the primary electronic chip 100 of the set of electronic chips can be a master circuit and it makes it possible to synchronize the operations of all the control circuits 107, then called control circuits slaves, other electronic chips in the electronic chip assembly (ie the intermediate electronic chip(s) and the last electronic chip of the corresponding series) in the sense that the control circuits 107 of the other electronic chips can be electrically connected in series from the control circuit 107 of the primary electronic chip 100th.
• its chaining input 115 is connected to its control circuit 107 and its chaining output 112 is connected to its control circuit which then makes it possible to ensure the desired synchronization.
• the circuit 107 for controlling the primary electronic chip 100 of the set of electronic chips is considered to be the master circuit because it is the only one to receive the global synchronization information for the set of corresponding electronic chips and that it initiates the scanning, ie that triggering the operation of the primary electronic chip 100th will induce the sequential propagation of the processing of the data received by the other electronic chips of said set of electronic chips chained in series from the primary electronic chip 100th.
• a 100e, lOOf, 100g electronic chip of the set of electronic chips has finished its work and when a following electronic chip in the series is present, it sends, preferably automatically, the chaining signal.
• the control circuits 107 are then, apart from the circuit 107 for controlling the primary electronic chip 100th, are almost inactive, that is to say they each have reduced functionality compared to the circuit 107 for controlling the 100th primary electronic chips.
• the chaining input 115 can be electrically connected to the control circuit 107 and to the first and second circuits 101, 102 (not shown).
• the master circuit can directly send the chaining signal which controls/commands the tasks of the slave circuits.
• the master circuit indicates by a change of state of the chaining signal that the electronic chip concerned must start working. Therefore, for a given set of electronic chips, the electronic chip which comprises the master circuit is connected to all the other electronic chips of said set of electronic chips in order to appropriately control the synchronization of said other electronic chips by sending a specific synchronization signal for each of said other electronic chips.
• the master circuit can count the number of clock ticks corresponding to the number of activated stages in each microchip of the microchip set.
• Concerning the display 1000 it may include an image processing chip 1002 configured to:
• first control signals 1003 via the first data bus 1006 of the display 1000, to the electronic chips 100a whose first circuits 101 are active, these first control signals 1003 including at least vertical synchronization data generated by the image processing chip 1002;
• the first data mentioned above include, or are constituted by, the first control signals
• the second data mentioned above include, or are constituted by, the display data and the second control signals.
• the electronic chip 100 as described finds an industrial application in the field of electronic chips 100 with several integrated functions which can be partially or entirely activated.
• an electronic chip 100 can be used, as mentioned above, as an integrated display chip comprising at least one pixel line control circuit and a pixel column control circuit in which no Any one of the pixel row driver circuit and the pixel column driver circuit can be activated either software or hardware.
• the electronic chip 100 as described has the following advantages:

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• 2022
  • 2022-06-30 FR FR2206664A patent/FR3137486B1/fr active Active
• 2023
  • 2023-06-27 WO PCT/FR2023/050976 patent/WO2024003501A1/fr not_active Ceased
  • 2023-06-27 EP EP23744531.7A patent/EP4548334A1/de active Pending

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