Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
  • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
  • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
  • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
  • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
  • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
  • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
  • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
  • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
  • H10P52/40—Chemomechanical polishing [CMP]
  • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/06—Planarisation of inorganic insulating materials
  • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step

Definitions

• the invention relates to a structure comprising a surface layer transferred onto a support provided with a charge trapping layer, the structure being capable of limiting pollution of the charge trapping layer by contaminants.
• the invention extends to a method of manufacturing this structure.
• Integrated devices are usually produced on wafer-shaped substrates, which mainly serve as support for their manufacturing.
• the increase in the degree of integration and the expected performances of these devices lead to an increasingly important coupling between their performances and the characteristics of the substrate on which they are formed. This is particularly the case for radio frequency (RF) devices, processing signals whose frequency is between approximately 3kHz and 300GHz, which find their application in particular in the field of telecommunications (telephony, Wi-Fi, Bluetooth, etc.).
• RF radio frequency
• crosstalk As an example of device/substrate coupling, the electromagnetic fields, resulting from high frequency signals propagating in the devices, penetrate into the depth of the substrate and interact with any electrical charge carriers found there. This results in unnecessary consumption of part of the signal energy through insertion loss and possible influences between components through crosstalk (“crosstalk” according to Anglo-Saxon terminology).
• HR SOI highly resistive insulator
• the support substrate may also include a charge trapping layer which will be placed on the side of the dielectric layer, preferably in contact with it.
• the trapping layer may include undoped polycrystalline silicon.
• a corresponding mechanical signal (that is to say an oscillation or a vibration) is generated at this material: the electrical signal is translated into a mechanical signal having a frequency dependence in relation to the alternating electrical signal, a dependence which is a function of the characteristics of the electrode(s), the properties of the ferroelectric material and other factors including the characteristics of the semiconductor support of the device.
• a dielectric layer interposed between the ferroelectric layer and its support makes it possible to improve the mechanical behavior of the transducer, and more particularly to limit the appearance of parasitic responses, induced losses linked to the properties of the substrate and interface effects within stacking. Increasing working frequencies may require thinning of the dielectric layer for purely mechanical reasons.
• the charge trapping layer by capturing possible electric charge carriers, limits interactions with the electromagnetic fields resulting from high frequency signals from the devices formed on the substrate and allows these devices to achieve high levels of performance.
• the thinning of the dielectric layers promotes the diffusion towards the trapping layer of charges of contaminating species such as hydrogen originally included in the surface layer or brought during the manufacture of the devices or lithium in the case of layer ferroelectric surface plates made of lithium niobate or lithium tantalate.
• the present invention aims to address, at least in part, this problem of contamination of the electrical charge trapping layer exacerbated by the thinness of the dielectric layer. It aims more particularly to propose a structure comprising a surface layer transferred to a support provided with an electrical charge trapping layer limiting contamination of the latter as well as a process allowing the manufacture of such a structure.
• the object of the invention is a device comprising a ferroelectric surface layer containing lithium; a dielectric layer comprising an oxide and disposed in contact with the ferroelectric surface layer; and a substrate in contact with the dielectric layer, the substrate comprising a charge trapping layer disposed on a support, the charge trapping layer being disposed between the support and the dielectric layer, device in which the dielectric layer has a thickness comprised between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a concentration of nitrogen in the dielectric layer and a surface roughness of the charge trapping layer are such that the charge trapping layer has a lithium dose of less than 5.10 11 at/cm 2 .
• An advantage of the structure according to the invention is to maintain the effectiveness of the trapping function of the electrical charge trapping layer even when the dielectric layer separating the charge trapping layer from the surface layer is thinned, this avoiding its contamination by chemical species likely to passivate charge trapping sites, in particular hydrogen and lithium present in the surface layer.
• the structure according to the invention makes it possible to provide substrates for the manufacture of components comprising piezoelectric layers and designed to operate at high frequencies and having excellent performance.
• the dielectric layer may have a thickness of between 150 nm and 250 nm;
• the nitrogen concentration of the dielectric layer can be between 10 21 at/cm 3 and 6.10 21 at/cm 3 ;
• the dielectric layer may be a layer of silicon oxide and a hydrogen concentration of the dielectric layer may be strictly lower than the nitrogen concentration of the dielectric layer;
• a hydrogen concentration of the dielectric layer (16) can be at least three times lower than the nitrogen concentration of the dielectric layer;
• a hydrogen concentration in the dielectric layer may be less than 10 22 at/cm 3 ;
• the lithium dose in the charge trapping layer may be less than 10 11 at/cm 2 ;
• the ferroelectric surface layer may comprise lithium niobate or lithium tantalate;
• the charge trapping layer may comprise polycrystalline silicon
• the ferroelectric surface layer may consist of a monocrystalline material.
• a second aspect of the invention relates to a method of manufacturing a device comprising a ferroelectric layer, comprising the steps of forming a charge trapping layer on a support to form a substrate; smoothing an exposed surface of the trapping layer so as to reduce a roughness of this exposed surface below a threshold roughness; forming a dielectric layer at least on the smoothed charge trapping layer and optionally on a donor substrate comprising a ferroelectric material, the dielectric layer having a thickness of between 150 nm and 500 nm; assembling the donor substrate and the substrate via the dielectric layer; removing part of the donor substrate to form a ferroelectric surface layer, the threshold roughness and a concentration of nitrogen in an oxide layer included in the dielectric layer being chosen so that the dose of lithium in the charge trapping layer is less than 5.10 11 at/cm 2 at the end of the manufacturing process.
• the nitrogen concentration of the dielectric layer can be between 5.10 20 at/cm 3 and 10 22 at/cm 3 ; and the surface roughness of the trapping layer may be less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm;
• the smoothing step may include mechanical-chemical polishing of the charge trapping layer
• the charge trapping layer may comprise polycrystalline silicon
• the manufacturing process may include the formation of a weakening plane by implantation of light species in the donor substrate to define the surface layer, and the step of eliminating part of the donor substrate may include detachment of the surface layer at the level of the weakening plane.
• a structure 1 comprising a substrate 10 integrating a support 12 and a layer 14 for trapping electrical charges on the support, a surface layer 20 placed on the substrate 10, and a dielectric layer 16 interposed between the surface layer 20 and the substrate 10 , preferably in direct contact with the surface layer 20 and the charge trapping layer 14.
• the surface layer 20 is a layer making it possible to give functions, for example piezoelectric, to a device developed on or in the structure 1.
• structure 1 can be in the form of a circular plate whose diameter can be 100, 200, 300 or even 450mm.
• structure 1 can be produced in multiple ways.
• structure 1 can be produced by a manufacturing process comprising the assembly of the substrate 10 and a donor substrate, the dielectric layer 16 being interposed between these two elements, followed by a step of eliminating a part of the donor substrate to form the surface layer 20.
• the step of eliminating part of the donor substrate can be carried out by mechanical-chemical thinning of this substrate.
• the structure 1 is preferentially manufactured by application of Smart CutTM technology, according to which a layer intended to form the surface layer 20 is delimited by means of a weakening plane formed by implantation of light species such as hydrogen in the donor substrate. This layer is then separated from the donor substrate stuck to the support via the dielectric layer 16, by fracture at the level of the weakening plane, the surface layer 20 remaining fixed on the substrate 10 provided with the trapping layer 14, with the dielectric layer 16 interposed between them.
• the substrate 10 typically has a thickness of several hundred microns.
• the substrate has a high resistivity, greater than 1000 ohm.centimeter, and even more preferably, greater than 2000 ohm.centimeter. This limits the density of charges, holes or electrons, which are likely to move in the substrate.
• the invention is not limited to a substrate 10 having such a resistivity, and it also provides RF performance advantages when the substrate has a more consistent resistivity, of the order of a few hundred ohm.centimeter, for example less than 1000 ohm.cm, or 500 ohm.cm or even 10 ohm.cm.
• the support 12 is preferably made of monocrystalline silicon. It may for example be a CZ silicon substrate with a low interstitial oxygen content of between 6 and 10 ppm, or an FZ silicon substrate which notably has a naturally very low interstitial oxygen content. It may also be a CZ silicon substrate having a high amount of interstitial oxygen (referred to as “High Oi”) greater than 26 ppm.
• the support 12 can alternatively be formed from another material: it can for example be sapphire, glass, quartz, silicon carbide, etc. In certain circumstances, and in particular when the trapping layer 14 has a sufficient thickness , for example greater than 30 microns, the support 12 can have a standard resistivity, less than 1 kohm.cm.
• the trapping layer 14 can be of very varied natures, as reported in the documents forming the state of the art. Generally speaking, it is a non-crystalline layer presenting structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores, etc. These structural defects form traps for the charges likely to circulate in the material, for example at the level of incomplete or dangling chemical bonds. This prevents or limits conduction in the trapping layer which consequently has a high resistivity.
• this trapping layer 14 is formed of a layer of polycrystalline silicon. Its thickness, particularly when it is formed on a resistive support 12, can be between 0.3 and 3 ⁇ m. But other thicknesses less than or greater than this interval are entirely possible, depending on the level of RF performance expected from structure 1.
• an amorphous layer made of silicon dioxide for example, on the support 12 before deposition of the trapping layer. of charges 14.
• the trapping layer 14 can be formed by implantation of a heavy species, such as argon, in a superficial thickness of the support 12, in order to form the structural defects constituting the electrical traps.
• This layer 14 can also be formed by porosification of a surface thickness of the support 12.
• the dielectric layer is usually made of silicon oxide and preferably contains nitrogen, favorable for forming a barrier layer preventing the diffusion of species, in particular hydrogen and lithium mentioned above.
• the surface layer 20 can be of any suitable nature. It is very preferably formed from a monocrystalline material. When structure 1 is intended to receive integrated semiconductor components, the surface layer 20 can thus be composed of monocrystalline silicon, or any other semiconductor material. In such a case, lithium contamination may originate from the equipment used to manufacture the structure. When structure 1 is intended to receive surface acoustic wave filters, surface layer 20 may be composed of a piezoelectric and/or ferroelectric material, such as lithium tantalate or lithium niobate. In this case, in addition to possible contamination from the outside, the lithium contamination also has its origin in the surface layer itself. The surface layer 20 can also include finished or semi-finished integrated components, formed on the donor substrate and transferred to the substrate 10 during the step of manufacturing the structure 1. Generally speaking, the thin layer can have a thickness between 10 nm and 10 ⁇ m.
• a charge trapping layer 14 in polycrystalline silicon is formed by deposition, for example using an LPCVD technique carried out between 600°C and 650°C.
• the trapping layer 14 has a thickness of approximately 500 nm, or even 1 micron.
• the trapping layer 14 is then polished by a chemical-mechanical polishing step (or CMP for Chemical-Mechanical Polishing in English terminology) leading to a removal of approximately 100 to 200 nanometers of the trapping layer, resulting in a layer of thickness between 500 and 1000 nanometer to present a surface roughness less than 300 nm, preferably less than 140 nm, or even more preferably less than 100 nm, in peak-valley measurement.
• a peak-valley roughness of 800 nm can be obtained with a deposition of a polycrystalline silicon charge trapping layer of several microns (approximately 4 ⁇ m).
• Such roughness could make it possible to avoid parasitic modes, in particular present in a POI (Piezoelectric-On-Insulator) type structure with a thickness of the piezoelectric layer greater than the wavelength used, due to the radiation of these modes of volumes within the volume and their interaction with the interfaces.
• a POI piezoelectric-On-Insulator
• a first annealing of this layer can be provided in an atmosphere poor in hydrogen (ie less than 5 ppm) at a temperature between the deposition temperature and 1000°C. .
• the temperature of the first annealing is greater than 620°C and preferably less than 900°C, for at least one hour and preferably for several hours.
• the hydrogen present in the trapping layer 3 is effectively exodused under these preferential annealing conditions to reduce its concentration below the threshold of 10 18 at/cm 3 , preferably 10 1 7 at/cm 3 , without deteriorating the polycrystalline nature of the trapping layer, by recrystallization effect.
• a dielectric layer 16 formed of a layer of silicon oxide including nitrogen of 300 is deposited, for example by a PECVD technique carried out at a temperature between 600°C and 800°C. nm to 1000 nm thick forming the dielectric layer 16 of structure 1.
• the layer is then polished by a chemical mechanical polishing (CMP) step leading to a removal of approximately 200 to 800 nanometers of the oxide to provide a surface having a roughness less than 0.3 nm RMS, for example on a field of 5*5 microns or a field of 30*30 microns by measurement by atomic force microscopy.
• CMP chemical mechanical polishing
• the dielectric layer 16 has a thickness of between 150 nm and 500 nm, preferably between 150 nm and 250 nm, and a significant hydrogen concentration of more than 10 20 at/cm 3 but preferably remaining lower than a nitrogen concentration. in the dielectric layer 16.
• a second annealing can be applied, similar to the first annealing described previously. It is therefore an annealing under an atmosphere poor in hydrogen (ie less than 5 ppm) and exposing the dielectric layer 16 to a temperature higher than its deposition temperature. It can be a neutral or oxidizing atmosphere. Preferably this temperature is greater than 800°C, typically between 800°C and 900°C. The annealing is continued for at least one hour, and preferably for several hours, finally to exo-diffuse the hydrogen from the dielectric layer 16, and possibly from the trapping layer 14.
• the layer dielectric 16 has a lower hydrogen concentration of 10 20 at/cm 3 and the trapping layer 14 has a lower hydrogen concentration of 10 18 at/cm 3 , preferably 10 1 7 at/cm 3 .
• a nitrogen concentration of between 5.10 20 at/cm 3 and 10 22 at/cm 3 allows, in combination with a trapping layer with roughness less than 800 nm, preferably less than 400 nm, preferably less than 100 nm, in peak-valley measurement, to obtain a sufficient barrier effect of the dielectric layer to develop on the substrate thus obtained devices capable to operate at high frequencies.
• the high values of the above ranges do not constitute an upper limit to the nitrogen concentration to obtain a barrier effect, but ensure a sufficiently low nitrogen concentration to be able to apply the structure according to the invention to known devices without risking to negatively influence their performance.
• each peak 310 of roughness of the trapping layer 14 creates one or more preferred paths (represented by straight arrows) for the migration of species through the dielectric layer 16 due to a local thinning of the dielectric layer 16 at the level of these peaks 310. is only a schematic representation used for explanatory purposes and in no way a realistic representation of the layers in a real device.
• a peak-valley measurement consists of measuring the sum Sum of a maximum depth S1 of a trough (the deepest valley) in a Surf surface considered and of a maximum height S2 of a peak (the deepest projection high) of this surface, the depth and height being measured relative to an average altitude Avg of this surface, for example on a given surface of the sample.
• a measurement by atomic force microscopy we can for example consider an observation surface corresponding to a square of 30 ⁇ m side, but we could alternatively consider a square of 5 ⁇ m side or more to establish the peak-valley measurement.
• the thickness of the oxide layer forming the dielectric layer 16 is measured between the average depth of the charge trapping layer and the surface of the oxide layer.
• dose we mean the quantity of atoms of a given chemical species over the thickness of the layer, that is to say the quantity contained in a volume defined by a given surface area on the surface of the layer and the projection of this surface perpendicular to the layer.
• a dose can be expressed in number of atoms per unit surface area of the layer.
• Tk of the oxide layer expressed in nanometers
• on the ordinate is the roughness in peak-valley measurement of the charge trapping layer indicated by PV and expressed in nanometers.
• the curves identified by [N] 1 , [N] 2 , [N] 3 and [N] 4 represent the minimum thicknesses of the oxide layer according to PV to obtain a maximum acceptable lithium dose set at 5.10 11 lithium atoms per square centimeter in the charge trapping layer, respectively for nitrogen concentrations of approximately 10 20 , 1.10 2 1 , 3.10 21 and 10 2 2 at/cm 3 , respectively.
• a PV value of 0 corresponds to a perfectly smooth charge trapping layer, which gives the minimum thickness of oxide to be deposited to sufficiently limit the diffusion of chemical species in the layer, lithium in particular, for a concentration of given nitrogen of this oxide.
• the oxide layer forming the dielectric layer 16 has a proportion between the concentrations of nitrogen and hydrogen which is favorable for blocking the diffusion of hydrogen, with an excess of nitrogen relative to the quantity of hydrogen, that is to say a ratio between the concentrations of nitrogen and hydrogen which is strictly greater than 1, preferably greater than 1.5, and even more preferably greater than 3, for concentrations measured by a SIMS method (Secondary Ion Mass Spectrometry in English terminology).
• the hydrogen concentration in the dielectric layer is preferably less than about 10 22 at/cm 3 , more preferably less than about 10 21 at/cm 3 , even more preferably less than about 10 20 at/cm 3 .
• the dielectric layer 16 is formed on the trapping layer 14, and these two layers have been deposited at relatively low temperature as has just been explained, it is not necessary to apply respectively the first and second annealing after each deposition step. It is possible to carry out a single annealing, under conditions similar to the first and second annealing, after the formation of the dielectric layer 16 at low temperature on the trapping layer 14. In other words, it is not necessary in this case to apply a specific annealing of the trapping layer 14 before the deposition of the dielectric layer 16.
• this embodiment it is generally preferred to place the dielectric layer 16 on the support 12 (via the trapping layer 14) rather than on the donor substrate 200.
• this support 12 may have a weakening plane, or be composed of a ferroelectric material having a Curie temperature relatively low or include components, which, in each of these cases, limits the thermal budget applicable to it to a few hundred degrees for a relatively short time, less than 1 hour.
• the invention does not exclude that, in certain favorable cases, the dielectric layer 16 may be formed at least in part on the donor substrate 200.
• hydrogen ions are implanted in a ferroelectric donor substrate 200 of lithium tantalate through a first 210 of its faces in order to form a buried weakening plane 220.
• a ferroelectric donor substrate 200 of lithium tantalate Parallel to the preparation of the substrate 10, hydrogen ions are implanted in a ferroelectric donor substrate 200 of lithium tantalate through a first 210 of its faces in order to form a buried weakening plane 220.
• the donor substrate obtained at this stage is illustrated in (b) of the .
• the donor substrate 200 is assembled with the silicon oxide layer 16 placed on the support 12 as illustrated in (c) of the , and the donor substrate 200 is then fractured at the weakening plane 220 using a moderate heat treatment of around 400°C.
• the complementary layer 22 is released from the donor substrate to expose a free face 230 of this layer which can then be prepared to improve its crystalline quality and surface condition.
• This preparation includes a step of thinning the first layer by mechanical-chemical polishing and a heat treatment step at 500°C in a neutral atmosphere for 1 hour.
• the structure obtained, indicated in (d) of the is that of the .
• ferroelectric layer of lithium tantalate used as surface layer 20
• other types of ferroelectric or piezoelectric materials such as lithium niobate could be used.
• a semiconductor surface layer such as a layer of silicon or comprising silicon such as monocrystalline silicon could be used.
• the manufacturing process detailed above therefore makes it possible to obtain a structure whose pollution of the trapping layer by damaging species, in particular hydrogen and lithium, remains sufficiently limited to develop devices capable of operating satisfactorily. at high frequencies.
• a nitrogen content between 5.10 20 at/cm 3 and 10 22 at/cm 3 for an oxide layer of sufficient thickness placed directly on a surface of a trapping layer 14 of roughness less than 300 nm in peak-valley measurement results in maintenance in the charge trapping layer 14 of lithium dose at less than 5.10 11 at/cm 2 , and hydrogen concentrations at less than 10 20 at /cm 3 , preferably less than 10 19 at/cm 3 , even more preferably less than 10 18 at/cm 3 .

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