TW202445754A - 包含表面層之結構及其製作方法,該表面層係接合至具有限污染之電荷捕捉層的載體上 - Google Patents
包含表面層之結構及其製作方法,該表面層係接合至具有限污染之電荷捕捉層的載體上 Download PDFInfo
- Publication number
- TW202445754A TW202445754A TW113100200A TW113100200A TW202445754A TW 202445754 A TW202445754 A TW 202445754A TW 113100200 A TW113100200 A TW 113100200A TW 113100200 A TW113100200 A TW 113100200A TW 202445754 A TW202445754 A TW 202445754A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- dielectric layer
- charge trapping
- substrate
- trapping layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
- H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P52/40—Chemomechanical polishing [CMP]
- H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/06—Planarisation of inorganic insulating materials
- H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Laminated Bodies (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2300760A FR3145444B1 (fr) | 2023-01-27 | 2023-01-27 | Structure comprenant une couche superficielle reportee sur un support muni d’une couche de piegeage de charges a contamination limitee et procede de fabrication |
| FRFR2300760 | 2023-01-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW202445754A true TW202445754A (zh) | 2024-11-16 |
Family
ID=86942393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW113100200A TW202445754A (zh) | 2023-01-27 | 2024-01-03 | 包含表面層之結構及其製作方法,該表面層係接合至具有限污染之電荷捕捉層的載體上 |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP4655821A1 (de) |
| JP (1) | JP2026505018A (de) |
| KR (1) | KR20250141690A (de) |
| CN (1) | CN120548606A (de) |
| FR (1) | FR3145444B1 (de) |
| TW (1) | TW202445754A (de) |
| WO (1) | WO2024156465A1 (de) |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1087041B1 (de) | 1999-03-16 | 2009-01-07 | Shin-Etsu Handotai Co., Ltd | Herstellungsverfahren für siliziumwafer und siliziumwafer |
| FR2838865B1 (fr) | 2002-04-23 | 2005-10-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee |
| FR2860341B1 (fr) | 2003-09-26 | 2005-12-30 | Soitec Silicon On Insulator | Procede de fabrication de structure multicouche a pertes diminuees |
| FR2933233B1 (fr) | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat de haute resistivite bon marche et procede de fabrication associe |
| FR2953640B1 (fr) | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
| US9768056B2 (en) | 2013-10-31 | 2017-09-19 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition |
| FR3094573B1 (fr) | 2019-03-29 | 2021-08-13 | Soitec Silicon On Insulator | Procede de preparation d’une couche mince de materiau ferroelectrique |
| FR3098642B1 (fr) | 2019-07-12 | 2021-06-11 | Soitec Silicon On Insulator | procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges |
| JP7610283B2 (ja) | 2019-11-26 | 2025-01-08 | クラリックス・イメージング・コーポレーション | 組織試料の術中体積測定撮像用の改善されたシステムおよび可視化方法 |
| JP2021180465A (ja) * | 2020-05-15 | 2021-11-18 | 信越化学工業株式会社 | 表面弾性波デバイス用複合基板及びその製造方法 |
-
2023
- 2023-01-27 FR FR2300760A patent/FR3145444B1/fr active Active
- 2023-12-29 CN CN202380091355.3A patent/CN120548606A/zh active Pending
- 2023-12-29 JP JP2025543229A patent/JP2026505018A/ja active Pending
- 2023-12-29 EP EP23840763.9A patent/EP4655821A1/de active Pending
- 2023-12-29 WO PCT/EP2023/087972 patent/WO2024156465A1/fr not_active Ceased
- 2023-12-29 KR KR1020257019359A patent/KR20250141690A/ko active Pending
-
2024
- 2024-01-03 TW TW113100200A patent/TW202445754A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR20250141690A (ko) | 2025-09-29 |
| CN120548606A (zh) | 2025-08-26 |
| WO2024156465A1 (fr) | 2024-08-02 |
| FR3145444A1 (fr) | 2024-08-02 |
| JP2026505018A (ja) | 2026-02-10 |
| EP4655821A1 (de) | 2025-12-03 |
| FR3145444B1 (fr) | 2025-11-21 |
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