EP4702589A1 - Procédé de préparation de substrat photonique et procédé de préparation ou de fabrication de guide d'ondes photonique - Google Patents

Procédé de préparation de substrat photonique et procédé de préparation ou de fabrication de guide d'ondes photonique

Info

Publication number
EP4702589A1
EP4702589A1 EP24726718.0A EP24726718A EP4702589A1 EP 4702589 A1 EP4702589 A1 EP 4702589A1 EP 24726718 A EP24726718 A EP 24726718A EP 4702589 A1 EP4702589 A1 EP 4702589A1
Authority
EP
European Patent Office
Prior art keywords
optical waveguide
substrate
copper
layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP24726718.0A
Other languages
German (de)
English (en)
Inventor
Marta DIVALL
Zheru QIU
Rui Ning WANG
Tobias Kippenberg
Xinru JI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ecole Polytechnique Federale de Lausanne EPFL
Original Assignee
Ecole Polytechnique Federale de Lausanne EPFL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ecole Polytechnique Federale de Lausanne EPFL filed Critical Ecole Polytechnique Federale de Lausanne EPFL
Publication of EP4702589A1 publication Critical patent/EP4702589A1/fr
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

Landscapes

  • Optical Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé de préparation ou de fabrication de dispositif de guide d'ondes optiques à circuit intégré photonique comprenant la fourniture d'un substrat de silicium, le dépôt d'au moins une couche ou un matériau de nitrure de silicium à piégeage de cuivre, le dépôt d'au moins une couche ou un matériau de gainage de guide d'ondes optique, la formation d'au moins un guide d'ondes optique ou d'une structure de guide d'ondes optique et le recuit thermique du ou des substrats de silicium après la formation du ou des guides d'ondes optiques ou de la structure de guide d'ondes optique sur le ou les substrats de silicium pour éliminer les impuretés d'hydrogène ou les impuretés liées à l'hydrogène du ou des guides d'ondes optiques, et pour capturer ou piéger les impuretés de cuivre du ou des substrats de silicium dans la ou les couches ou le ou les matériaux de nitrure de silicium à piégeage de cuivre.
EP24726718.0A 2023-04-25 2024-04-19 Procédé de préparation de substrat photonique et procédé de préparation ou de fabrication de guide d'ondes photonique Pending EP4702589A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP23169810 2023-04-25
PCT/IB2024/053818 WO2024224247A1 (fr) 2023-04-25 2024-04-19 Procédé de préparation de substrat photonique et procédé de préparation ou de fabrication de guide d'ondes photonique

Publications (1)

Publication Number Publication Date
EP4702589A1 true EP4702589A1 (fr) 2026-03-04

Family

ID=86226567

Family Applications (1)

Application Number Title Priority Date Filing Date
EP24726718.0A Pending EP4702589A1 (fr) 2023-04-25 2024-04-19 Procédé de préparation de substrat photonique et procédé de préparation ou de fabrication de guide d'ondes photonique

Country Status (2)

Country Link
EP (1) EP4702589A1 (fr)
WO (1) WO2024224247A1 (fr)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620632B2 (en) * 2000-04-06 2003-09-16 Seh America, Inc. Method for evaluating impurity concentrations in semiconductor substrates
JP2003017497A (ja) * 2001-07-04 2003-01-17 Nec Corp 半導体装置の製造方法
US20030104680A1 (en) * 2001-11-13 2003-06-05 Memc Electronic Materials, Inc. Process for the removal of copper from polished boron-doped silicon wafers
US7657390B2 (en) * 2005-11-02 2010-02-02 Applied Materials, Inc. Reclaiming substrates having defects and contaminants
JP6427946B2 (ja) * 2014-05-13 2018-11-28 株式会社Sumco エピタキシャルシリコンウェーハの製造方法、エピタキシャルシリコンウェーハ、および固体撮像素子の製造方法
KR20150134543A (ko) * 2014-05-22 2015-12-02 삼성전자주식회사 소자 제조용 기판 및 반도체 소자
US10191215B2 (en) 2015-05-05 2019-01-29 Ecole Polytechnique Federale De Lausanne (Epfl) Waveguide fabrication method
US11187532B2 (en) * 2020-03-06 2021-11-30 Anello Photonics, Inc. Process flow for fabricating integrated photonics optical gyroscopes
CN113506733A (zh) * 2021-06-22 2021-10-15 华虹半导体(无锡)有限公司 降低硅片金属杂质的方法
JP7487407B2 (ja) * 2021-09-30 2024-05-20 信越半導体株式会社 エピタキシャルウェーハの製造方法

Also Published As

Publication number Publication date
WO2024224247A1 (fr) 2024-10-31

Similar Documents

Publication Publication Date Title
Liang et al. Low-temperature, strong SiO2-SiO2 covalent wafer bonding for III–V compound semiconductors-to-silicon photonic integrated circuits
US7078351B2 (en) Photoresist intensive patterning and processing
CN100595891C (zh) 用于低k刻蚀后的无损灰化工艺和系统
US7595005B2 (en) Method and apparatus for ashing a substrate using carbon dioxide
KR101037308B1 (ko) 고-k 유전성 재료 에칭 방법 및 시스템
US7067435B2 (en) Method for etch-stop layer etching during damascene dielectric etching with low polymerization
CN113677825B (zh) 沟槽中薄膜沉积的方法
US6444588B1 (en) Anti-reflective coatings and methods regarding same
US20210098247A1 (en) Method for fabricating thick dielectric films using stress control
US6037270A (en) Method of manufacturing semiconductor device and methods of processing, analyzing and manufacturing its substrate
US20240210625A1 (en) Low Temperature Fabrication of Silicon Nitride Photonic Devices
Choi et al. Formation of plasma induced surface damage in silica glass etching for optical waveguides
EP4702589A1 (fr) Procédé de préparation de substrat photonique et procédé de préparation ou de fabrication de guide d'ondes photonique
US20050136681A1 (en) Method and apparatus for removing photoresist from a substrate
EP4689747A2 (fr) Procédé de fabrication de dispositif de guide d'ondes optique à basse température
KR100361195B1 (ko) 반도체 장치의 제조 방법
KR100394504B1 (ko) 절연막의 막질 개선방법 및 반도체 장치
US6933235B2 (en) Method for removing contaminants on a substrate
Boulard et al. Bevel contamination management in 3D integration by localized SiO2 deposition
WO2026088028A1 (fr) Dispositif de guide d'ondes, dispositif de guide d'ondes optique à circuit intégré photonique, procédé de fabrication d'un dispositif de guide d'ondes ou d'un dispositif de guide d'ondes optique à circuit intégré photonique, et générateur de lumière pour générer de la lumière soliton ou des impulsions optiques soliton
KR100248159B1 (ko) 반도체장치에 있어서 이온주입을 통한 에스오지층형성방법
KR100240927B1 (ko) 반도체 기판의 평탄화 방법
WO2024231800A1 (fr) Guide d'ondes de nitrure de silicium ou procédé de fabrication de circuit intégré photonique
JPH10300963A (ja) 光導波路の形成方法
Ji et al. Wafer-scale Manufacturing of Ultra-low Loss, High-density Si 3 N 4 Photonic Integrated Circuits

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20251114

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR