EP4702594A1 - Dispositif à circuit intégré empilé comprenant un dispositif condensateur intégré - Google Patents

Dispositif à circuit intégré empilé comprenant un dispositif condensateur intégré

Info

Publication number
EP4702594A1
EP4702594A1 EP24715337.2A EP24715337A EP4702594A1 EP 4702594 A1 EP4702594 A1 EP 4702594A1 EP 24715337 A EP24715337 A EP 24715337A EP 4702594 A1 EP4702594 A1 EP 4702594A1
Authority
EP
European Patent Office
Prior art keywords
die
stacked
icd
contacts
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP24715337.2A
Other languages
German (de)
English (en)
Inventor
Darko Popovic
Miguel Miranda Corbalan
Durodami Lisk
Yue Li
Irfan Khan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/454,388 external-priority patent/US20240363605A1/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP4702594A1 publication Critical patent/EP4702594A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

Un dispositif à circuit intégré (CI) empilé comprend une première puce comprenant des circuits actifs et un réseau de distribution d'énergie (PDN). La première puce comporte un premier ensemble de contacts sur un premier côté de la première puce. Le dispositif à CI empilé comprend également une seconde puce couplée, sur un premier côté de la seconde puce, au premier côté de la première puce. La seconde puce comprend également, sur un second côté de la seconde puce, un second ensemble de contacts pour connecter électriquement des circuits de la seconde puce à un substrat. Le dispositif à CI empilé comprend également un dispositif condensateur intégré (ICD) couplé au premier côté de la première puce. L'ICD est électriquement connecté, via le premier ensemble de contacts, au PDN et comprend un ou plusieurs conducteurs traversant l'ICD pour connecter électriquement le PDN au substrat.
EP24715337.2A 2023-04-28 2024-02-26 Dispositif à circuit intégré empilé comprenant un dispositif condensateur intégré Pending EP4702594A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202363498978P 2023-04-28 2023-04-28
US18/454,388 US20240363605A1 (en) 2023-04-28 2023-08-23 Stacked integrated circuit device including integrated capacitor device
PCT/US2024/017218 WO2024226151A1 (fr) 2023-04-28 2024-02-26 Dispositif à circuit intégré empilé comprenant un dispositif condensateur intégré

Publications (1)

Publication Number Publication Date
EP4702594A1 true EP4702594A1 (fr) 2026-03-04

Family

ID=90571595

Family Applications (1)

Application Number Title Priority Date Filing Date
EP24715337.2A Pending EP4702594A1 (fr) 2023-04-28 2024-02-26 Dispositif à circuit intégré empilé comprenant un dispositif condensateur intégré

Country Status (5)

Country Link
EP (1) EP4702594A1 (fr)
KR (1) KR20260007188A (fr)
CN (1) CN120958579A (fr)
TW (1) TW202445826A (fr)
WO (1) WO2024226151A1 (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779849B2 (en) * 2012-01-27 2014-07-15 Micron Technology, Inc. Apparatuses and methods for providing capacitance in a multi-chip module
US8653626B2 (en) * 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
MY186309A (en) * 2014-03-28 2021-07-07 Intel Corp Tsv-connected backside decoupling
WO2017052471A1 (fr) * 2015-09-23 2017-03-30 Nanyang Technological University Dispositifs à semi-conducteur et leurs procédés de formation
MY202342A (en) * 2017-06-08 2024-04-24 Intel Corp Over-molded ic package with in-mold capacitor
US11784215B2 (en) * 2020-03-02 2023-10-10 Google Llc Deep trench capacitors embedded in package substrate
US11626359B2 (en) * 2021-04-27 2023-04-11 Qualcomm Incorporated Three-dimensional integrated circuit (3D IC) power distribution network (PDN) capacitor integration

Also Published As

Publication number Publication date
WO2024226151A1 (fr) 2024-10-31
KR20260007188A (ko) 2026-01-13
TW202445826A (zh) 2024-11-16
CN120958579A (zh) 2025-11-14

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