EP4732479A1 - Séquence de bits pouvant être transmise efficacement avec disparité restreinte et correction d'erreur directe - Google Patents
Séquence de bits pouvant être transmise efficacement avec disparité restreinte et correction d'erreur directeInfo
- Publication number
- EP4732479A1 EP4732479A1 EP24709069.9A EP24709069A EP4732479A1 EP 4732479 A1 EP4732479 A1 EP 4732479A1 EP 24709069 A EP24709069 A EP 24709069A EP 4732479 A1 EP4732479 A1 EP 4732479A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- bit
- data
- disparity
- segments
- forward error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Probability & Statistics with Applications (AREA)
- Dc Digital Transmission (AREA)
- Error Detection And Correction (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
La présente invention concerne un procédé de génération d'une séquence de bits qui peut être transmise efficacement et présente une disparité limitée ainsi qu'une longueur d'exécution limitée. Le procédé de l'invention permet de transmettre des données sur un canal de transmission de manière particulièrement efficace. Par rapport à l'état de la technique, l'invention offre, entre autres, l'avantage que le comportement physique sur un canal de transmission peut constamment être commandé de manière déterministe malgré une réduction des exigences de ressources. Ainsi, selon le procédé de l'invention, les erreurs binaires sont minimales et une erreur de transmission peut être corrigée efficacement, c'est-à-dire avec un effort technique minimal. En outre, les codeurs utilisés sont conçus avec un nombre minimal de portes et le procédé de l'invention comprend implicitement une forme d'imbrication permettant de corriger de manière particulièrement avantageuse les erreurs dites de rafales.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP23180790.0A EP4236132A3 (fr) | 2023-06-21 | 2023-06-21 | Séquence binaire pouvant être transmise efficace avec disparité réduite et correction d'erreurs sans voie de retour codée par ligne |
| PCT/EP2024/055992 WO2024260592A1 (fr) | 2023-06-21 | 2024-03-07 | Séquence de bits pouvant être transmise efficacement avec disparité restreinte et correction d'erreur directe |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP4732479A1 true EP4732479A1 (fr) | 2026-04-29 |
Family
ID=86942909
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP23180790.0A Pending EP4236132A3 (fr) | 2023-06-21 | 2023-06-21 | Séquence binaire pouvant être transmise efficace avec disparité réduite et correction d'erreurs sans voie de retour codée par ligne |
| EP24709069.9A Pending EP4732479A1 (fr) | 2023-06-21 | 2024-03-07 | Séquence de bits pouvant être transmise efficacement avec disparité restreinte et correction d'erreur directe |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP23180790.0A Pending EP4236132A3 (fr) | 2023-06-21 | 2023-06-21 | Séquence binaire pouvant être transmise efficace avec disparité réduite et correction d'erreurs sans voie de retour codée par ligne |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20260113145A1 (fr) |
| EP (2) | EP4236132A3 (fr) |
| KR (1) | KR20260007248A (fr) |
| CN (1) | CN121359404A (fr) |
| WO (1) | WO2024260592A1 (fr) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4486739A (en) * | 1982-06-30 | 1984-12-04 | International Business Machines Corporation | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code |
| GB8912471D0 (en) * | 1989-05-31 | 1989-07-19 | Int Computers Ltd | Data transmission code |
| US5440347A (en) * | 1993-05-07 | 1995-08-08 | Philips Electronics North America Corporation | Method and apparatus for randomizing training sequences to minimize interference in digital transmissions |
| US5398237A (en) * | 1993-05-26 | 1995-03-14 | Gi Corporation | Acquisition and tracking of independent quadrature modulated bitstreams |
| US7296211B2 (en) * | 2002-06-25 | 2007-11-13 | Lockheed Martin Corporation | System and method for transferring data on a data link |
| US7103830B1 (en) * | 2002-12-18 | 2006-09-05 | Applied Micro Circuits Corporation | DC balanced error correction coding |
| US9379846B1 (en) * | 2014-12-19 | 2016-06-28 | Cadence Design Systems, Inc. | System and method of encoding in a serializer/deserializer |
| DE102015111465A1 (de) | 2015-07-15 | 2017-01-19 | Inova Semiconductors Gmbh | Verfahren, Vorrichtung und System zum empfängerseitigen Bestimmen eines Abtastzeitpunkts |
-
2023
- 2023-06-21 EP EP23180790.0A patent/EP4236132A3/fr active Pending
-
2024
- 2024-03-07 KR KR1020257040462A patent/KR20260007248A/ko active Pending
- 2024-03-07 CN CN202480041483.1A patent/CN121359404A/zh active Pending
- 2024-03-07 WO PCT/EP2024/055992 patent/WO2024260592A1/fr not_active Ceased
- 2024-03-07 EP EP24709069.9A patent/EP4732479A1/fr active Pending
-
2025
- 2025-12-18 US US19/425,573 patent/US20260113145A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024260592A1 (fr) | 2024-12-26 |
| EP4236132A3 (fr) | 2024-01-03 |
| US20260113145A1 (en) | 2026-04-23 |
| KR20260007248A (ko) | 2026-01-13 |
| CN121359404A (zh) | 2026-01-16 |
| EP4236132A2 (fr) | 2023-08-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
| 17P | Request for examination filed |
Effective date: 20251204 |
|
| AK | Designated contracting states |
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