ES2008114A6 - Procesador celular de instruccion unica y datos multiples (simo) que emplea logica de multiples estados para la conexion a buses de datos. - Google Patents

Procesador celular de instruccion unica y datos multiples (simo) que emplea logica de multiples estados para la conexion a buses de datos.

Info

Publication number
ES2008114A6
ES2008114A6 ES8603405A ES8603405A ES2008114A6 ES 2008114 A6 ES2008114 A6 ES 2008114A6 ES 8603405 A ES8603405 A ES 8603405A ES 8603405 A ES8603405 A ES 8603405A ES 2008114 A6 ES2008114 A6 ES 2008114A6
Authority
ES
Spain
Prior art keywords
coupling
processing apparatus
buses
collection
data buses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8603405A
Other languages
English (en)
Inventor
Steven Gregory Morton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Publication of ES2008114A6 publication Critical patent/ES2008114A6/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2051—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant in regular structures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Microcomputers (AREA)

Abstract

PROCESADOR CELULAR DE INSTRUCCION UNICA Y DATOS MULTIPLES (SIMD) QUE EMPLEA LOGICA DE MULTIPLES ESTADOS PARA LA CONEXION A BUSES DE DATOS. SE DESCRIBE UN DISPOSITIVO PARA UN PROCESADOR CELULAR CAPAZ DE UTILIZAR LOGICA DE 5 NIVELES, QUE COMPRENDE UN ESTADO DE DESCONEXION DE FORMA QUE UNA COLECCION DE DISPOSITIVOS SIMILARES PUEDAN CONECTARSE A UN BUS COMUN, PUDIENDO CADA UNO DE ELLOS ACTIVAR EL BUS Y 4 NIVELES LOGICOS QUE SE REPRESENTAN EN EL BUS POR 4 NIVELES DE TENSION. ESTOS NIVELES DE TENSION LOS RECIBE UN CONVERTIDOR A/D DE 2-BITIOS Y LOS GENERA UN CONVERTIDOR D/A DE 2-BITIOS, OPTIMIZADO PARA MINIMA DISIPACION DE ENERGIA. SE DESCRIBE ADEMAS UNA DISPOSICION EN LA QUE UNA AGRUPACION DETERMINADA PUEDE ORGANIZARSE EN UNA ESTRUCTURA REGULAR PARA MINIMIZAR EL ALAMBRADO DE INTERCONEXION EN LA PASTILLA DE FORMA QUE PUEDA SOPORTAR UNA MULTITUD DE BUSES EXTERNOS QUE SON MULTIPLEXADOS EN UN UNICO BUS INTERNO COMUN. SE DESCRIBE ADEMAS UNA DISPOSICION EN LA QUE ESTOS TERMINALES SE PUEDEN CONFIGURAR DINAMICAMENTE PARA FORMAR BUSES DE 2 NIVELES Y 4 NIVELES QUE SATISFAGAN LAS NECESIDADES DE INTERCONEXION DE LA PASTILLA.
ES8603405A 1985-12-12 1986-12-12 Procesador celular de instruccion unica y datos multiples (simo) que emplea logica de multiples estados para la conexion a buses de datos. Expired ES2008114A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/808,315 US4916657A (en) 1985-12-12 1985-12-12 Single instruction multiple data (SIMD) cellular array processing apparatus employing multiple state logic for coupling to data buses

Publications (1)

Publication Number Publication Date
ES2008114A6 true ES2008114A6 (es) 1989-07-16

Family

ID=25198439

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8603405A Expired ES2008114A6 (es) 1985-12-12 1986-12-12 Procesador celular de instruccion unica y datos multiples (simo) que emplea logica de multiples estados para la conexion a buses de datos.

Country Status (4)

Country Link
US (1) US4916657A (es)
EP (1) EP0236643A3 (es)
JP (1) JPS62138955A (es)
ES (1) ES2008114A6 (es)

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WO1991010967A1 (fr) * 1990-01-09 1991-07-25 Hajime Seki Systeme d'ordinateur electronique et son processeur d'operations
US5713037A (en) * 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
US5809292A (en) * 1990-11-13 1998-09-15 International Business Machines Corporation Floating point for simid array machine
US5794059A (en) * 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
ATE180586T1 (de) * 1990-11-13 1999-06-15 Ibm Paralleles assoziativprozessor-system
US5765011A (en) * 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5828894A (en) * 1990-11-13 1998-10-27 International Business Machines Corporation Array processor having grouping of SIMD pickets
US5588152A (en) * 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
US5734921A (en) * 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5625836A (en) * 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5963746A (en) * 1990-11-13 1999-10-05 International Business Machines Corporation Fully distributed processing memory element
US5590345A (en) * 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5815723A (en) * 1990-11-13 1998-09-29 International Business Machines Corporation Picket autonomy on a SIMD machine
US5630162A (en) * 1990-11-13 1997-05-13 International Business Machines Corporation Array processor dotted communication network based on H-DOTs
US5765015A (en) * 1990-11-13 1998-06-09 International Business Machines Corporation Slide network for an array processor
US5963745A (en) * 1990-11-13 1999-10-05 International Business Machines Corporation APAP I/O programmable router
US5617577A (en) * 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5966528A (en) * 1990-11-13 1999-10-12 International Business Machines Corporation SIMD/MIMD array processor with vector processing
US5765012A (en) * 1990-11-13 1998-06-09 International Business Machines Corporation Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine library
US5594918A (en) * 1991-05-13 1997-01-14 International Business Machines Corporation Parallel computer system providing multi-ported intelligent memory
US5625713A (en) * 1991-08-09 1997-04-29 Ricoh Corporation Apparatus and method for increasing the throughput of an acoustic or image compression system
JP2642039B2 (ja) * 1992-05-22 1997-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション アレイ・プロセッサ
US5864584A (en) * 1995-02-13 1999-01-26 International Business Machines Corporation Circuitry for allowing two drivers to communicate with two receivers using one transmission line
US5761246A (en) * 1995-08-14 1998-06-02 International Business Machines Corporation Circuit for multiplexing a plurality of signals on one transmission line between chips
US6058465A (en) * 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US6401189B1 (en) 1998-08-05 2002-06-04 Michael J. Corinthios General base state assignment for optimal massive parallelism
US6496961B2 (en) * 2000-10-27 2002-12-17 Nec Usa, Inc. Dynamic detection and removal of inactive clauses in SAT with application in image computation
US20070012758A1 (en) * 2005-07-14 2007-01-18 Wilson Wanda J Device and method for recording financial information
CN101713813B (zh) * 2008-10-06 2012-06-06 中兴通讯股份有限公司 片上系统芯片和对片上系统芯片进行测试的方法
KR102375054B1 (ko) * 2015-12-11 2022-03-17 에스케이하이닉스 주식회사 테스트 모드 설정회로 및 이를 포함하는 반도체 장치
CN113364910B (zh) * 2021-06-08 2022-09-02 Tcl通讯（宁波）有限公司 一种信号处理方法、装置、设备及存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US4425664A (en) * 1975-11-26 1984-01-10 Bell Telephone Laboratories, Incorporated Multiport programmable digital data set
US4139910A (en) * 1976-12-06 1979-02-13 International Business Machines Corporation Charge coupled device memory with method of doubled storage capacity and independent of process parameters and temperature
US4438491A (en) * 1980-10-14 1984-03-20 Constant James N Computer having plural IC chips with each chip including a transceiver
US4523595A (en) * 1981-11-25 1985-06-18 Zibell J Scott Method and apparatus for automatic detection and treatment of ventricular fibrillation
JPS58115547A (ja) * 1981-12-29 1983-07-09 Fujitsu Ltd マイクロプロセツサの動作モ−ド設定方式

Also Published As

Publication number Publication date
US4916657A (en) 1990-04-10
EP0236643A3 (en) 1989-06-14
JPS62138955A (ja) 1987-06-22
EP0236643A2 (en) 1987-09-16

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Legal Events

Date Code Title Description
SA6 Expiration date (snapshot 920101)

Free format text: 2006-12-12