ES2035303T3 - Circuitos de enclavamiento cmos. - Google Patents

Circuitos de enclavamiento cmos.

Info

Publication number
ES2035303T3
ES2035303T3 ES198888307656T ES88307656T ES2035303T3 ES 2035303 T3 ES2035303 T3 ES 2035303T3 ES 198888307656 T ES198888307656 T ES 198888307656T ES 88307656 T ES88307656 T ES 88307656T ES 2035303 T3 ES2035303 T3 ES 2035303T3
Authority
ES
Spain
Prior art keywords
channel
latch circuit
transistor
true
complementary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198888307656T
Other languages
English (en)
Inventor
Donald Monroe Walters, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2035303T3 publication Critical patent/ES2035303T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Supporting Of Heads In Record-Carrier Devices (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

UN CIRCUITO INVERSOR CMOS QUE ELIMINA LA BAJADA DEL NIVEL DE ALTO VOLTAJE PROCEDENTE DE UN BUS DE DATOS DE PRECARGA/DESCARGA ORIGINADO POR UN EFECTO DE CARGA COMPARTIDA. EL CIRCUITO INVERSOR CMOS ESTA FORMADO POR UN TRANSISTOR (P1) DE PRECARGA DE CANAL P, UN TRANSISTOR (P2) ACCIONADOR DE CANAL P, UN TRANSISTOR (N1) ACCIONADOR DE CANAL N, UN TRANSISTOR (N2) HABILITADOR DE CANAL N, Y UNA PUERTA DE TRANSMISION (TG) PARA CARGAR UNA SEÑAL DE ENTRADA DE DATOS COMPLEMENTARIOS EN UN NODO DE ALMACENAMIENTO (A) COMO RESPUESTA A SEÑALES DE CARGA COMPLEMENTARIAS Y VERDADERAS. EL CIRCUITO INVERSOR INCLUYE ADEMAS UNOS TRANSISTORES DE ENTRADA FORMADOS POR UN PAR DE TRANSISTORES DE ENTRADA DE CANAL P (P3,P4) Y UN PAR DE TRANSISTORES DE ENTRADA DE CANAL N (N3,N4) QUE ESTAN TODOS CONECTADOS EN SERIE, Y RESPONDEN A SEÑALES DE CARGA VERDADERAS Y COMPLEMENTARIAS Y A SEÑALES DE ENTRADA COMPLEMENTARIAS Y VERDADERAS PARA MANTENER AL CIRCUITO INVERSOR EN UNO DE DOS ESTADOS.
ES198888307656T 1987-11-02 1988-08-18 Circuitos de enclavamiento cmos. Expired - Lifetime ES2035303T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/115,279 US4800300A (en) 1987-11-02 1987-11-02 High-performance, CMOS latch for improved reliability

Publications (1)

Publication Number Publication Date
ES2035303T3 true ES2035303T3 (es) 1993-04-16

Family

ID=22360340

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198888307656T Expired - Lifetime ES2035303T3 (es) 1987-11-02 1988-08-18 Circuitos de enclavamiento cmos.

Country Status (7)

Country Link
US (1) US4800300A (es)
EP (1) EP0315301B1 (es)
JP (1) JP2733578B2 (es)
AT (1) ATE81738T1 (es)
DE (1) DE3875450T2 (es)
ES (1) ES2035303T3 (es)
GR (1) GR3006154T3 (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0520830A3 (en) * 1991-06-28 1993-03-17 Texas Instruments Incorporated Apparatus and method for ecl-like signal to cmos signal conversion
US5361229A (en) * 1993-04-08 1994-11-01 Xilinx, Inc. Precharging bitlines for robust reading of latch data
US5461331A (en) * 1994-07-28 1995-10-24 International Business Machines Corporation Dynamic to static logic translator or pulse catcher
JP3229164B2 (ja) * 1994-07-28 2001-11-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ラッチ回路
US5576651A (en) * 1995-05-22 1996-11-19 International Business Machines Corporation Static/dynamic flip-flop
US5936449A (en) * 1997-09-08 1999-08-10 Winbond Electronics Corporation Dynamic CMOS register with a self-tracking clock
DE19743347C2 (de) * 1997-09-30 1999-08-12 Siemens Ag RS-Flip-Flop mit Enable-Eingängen
JP3533357B2 (ja) * 2000-02-29 2004-05-31 株式会社東芝 論理演算機能を備えた半導体集積回路
US7138850B1 (en) 2004-02-04 2006-11-21 Marvell Semiconductor Israel Ltd High-gain synchronizer circuitry and methods
US8786307B2 (en) * 2011-06-28 2014-07-22 Texas Instruments Incorporated Bias temperature instability-resistant circuits
US9178499B2 (en) * 2014-02-27 2015-11-03 Texas Instruments Incorporated Low-power offset-stored latch
TWI820090B (zh) * 2018-09-14 2023-11-01 日商鎧俠股份有限公司 半導體記憶裝置
US10867641B2 (en) 2018-09-14 2020-12-15 Toshiba Memory Corporation Data latch circuit and semiconductor memory device
CN113644907B (zh) * 2021-08-31 2023-07-07 复旦大学 由共栅互补场效应晶体管构建的d锁存器
US12278624B2 (en) * 2022-02-11 2025-04-15 Pratt & Whitney Canada Corp. Logic circuit for providing a signal value after a predetermined time period and method of using same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3739193A (en) * 1971-01-11 1973-06-12 Rca Corp Logic circuit
JPS5338373A (en) * 1976-09-20 1978-04-08 Seiko Epson Corp Ic for watch
US4506167A (en) * 1982-05-26 1985-03-19 Motorola, Inc. High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates
US4629909A (en) * 1984-10-19 1986-12-16 American Microsystems, Inc. Flip-flop for storing data on both leading and trailing edges of clock signal
US4617480A (en) * 1984-10-22 1986-10-14 Motorola, Inc. High speed data synchronizer which minimizes circuitry

Also Published As

Publication number Publication date
JP2733578B2 (ja) 1998-03-30
DE3875450T2 (de) 1993-04-22
US4800300A (en) 1989-01-24
DE3875450D1 (de) 1992-11-26
ATE81738T1 (de) 1992-11-15
EP0315301A3 (en) 1990-03-14
GR3006154T3 (es) 1993-06-21
JPH01130618A (ja) 1989-05-23
EP0315301A2 (en) 1989-05-10
EP0315301B1 (en) 1992-10-21

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