ES2039608T3 - Circuito integrado que comprende circuiteria logica. - Google Patents

Circuito integrado que comprende circuiteria logica.

Info

Publication number
ES2039608T3
ES2039608T3 ES198888300707T ES88300707T ES2039608T3 ES 2039608 T3 ES2039608 T3 ES 2039608T3 ES 198888300707 T ES198888300707 T ES 198888300707T ES 88300707 T ES88300707 T ES 88300707T ES 2039608 T3 ES2039608 T3 ES 2039608T3
Authority
ES
Spain
Prior art keywords
clock
integrated circuit
logic
current
circuiteria
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198888300707T
Other languages
English (en)
Inventor
Che-Tsung Chen
Chin-Jen Lin
Kevin David Kolwicz
Won Jae Yoon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of ES2039608T3 publication Critical patent/ES2039608T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Shift Register Type Memory (AREA)
  • Power Sources (AREA)
  • Measuring Fluid Pressure (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

UN CIRCUITO INTEGRADO QUE TIENE UN GRAN NUMERO DE ETAPAS CON PUERTAS LOGICAS PARA TRASMISION SE HA ENCONTRADO QUE SUFRE UNA GRAN PICO DE CORRIENTE AL CONECTARSE. ESTO ES DEBIDO AL NODO DE ENTRADA FLOTANTE DE LOS INVERSORES COMPLEMENTARIOS CAUSANDO QUE LA CORRIENTE FLUYA BREVEMENTE ANTES DE QUE EL PULSO DEL RELOJ LLEGUE. EL PRESENTE INVENTO PROPORCIONA UNA TENSION DE DC SOBRE LAS PUERTAS DE LOS TRANSISTORES DE PASO HASTA QUE LLEGA EL PULSO DEL RELOJ Y ELIMINANDO EL NODO FLOTANTE. SE PUEDE GENERAR UNA VENTANA PERIODICA OPCIONAL PARA EXAMINAR EL RELOJ DEL SISTEMA DESPUES DE ENCENDIDO, Y DETECTAR UNA PERDIDA DE LA CONDICION DEL RELOJ.
ES198888300707T 1987-02-04 1988-01-27 Circuito integrado que comprende circuiteria logica. Expired - Lifetime ES2039608T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/011,162 US4736119A (en) 1987-02-04 1987-02-04 Dynamic CMOS current surge control

Publications (1)

Publication Number Publication Date
ES2039608T3 true ES2039608T3 (es) 1993-10-01

Family

ID=21749137

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198888300707T Expired - Lifetime ES2039608T3 (es) 1987-02-04 1988-01-27 Circuito integrado que comprende circuiteria logica.

Country Status (8)

Country Link
US (1) US4736119A (es)
EP (1) EP0277767B1 (es)
JP (1) JPH073751B2 (es)
CA (1) CA1281088C (es)
DE (1) DE3879524T2 (es)
ES (1) ES2039608T3 (es)
HK (1) HK117093A (es)
SG (1) SG60193G (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2508697B2 (ja) * 1987-03-27 1996-06-19 日本電気株式会社 半導体集積回路
US5200907A (en) * 1990-04-16 1993-04-06 Tran Dzung J Transmission gate logic design method
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US5513358A (en) * 1994-02-04 1996-04-30 Motorola, Inc. Method and apparatus for power-up state initialization in a data processing system
US5537656A (en) * 1994-06-17 1996-07-16 Intel Corporation Method and apparatus for a microprocessor to enter and exit a reduced power consumption state
EP0709774A1 (en) * 1994-10-27 1996-05-01 STMicroelectronics S.r.l. Method and circuit for detecting a fault in a clock signal for microprocessor electronic devices including memory elements
US5983339A (en) * 1995-08-21 1999-11-09 International Business Machines Corporation Power down system and method for pipelined logic functions
JPH11213665A (ja) * 1998-01-26 1999-08-06 Mitsubishi Electric Corp 半導体回路装置およびその使用方法
US6317839B1 (en) * 1999-01-19 2001-11-13 International Business Machines Corporation Method of and apparatus for controlling supply of power to a peripheral device in a computer system
DE10346621A1 (de) * 2003-10-08 2005-05-04 Bosch Gmbh Robert Steuergerät
US8410833B2 (en) * 2011-02-28 2013-04-02 Advanced Micro Devices, Inc. On-chip power-up control circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165030A (en) * 1979-06-11 1980-12-23 Oki Electric Ind Co Ltd Signal transmission circuit of dynamic type
US4317180A (en) * 1979-12-26 1982-02-23 Texas Instruments Incorporated Clocked logic low power standby mode
JPS5881334A (ja) * 1981-11-11 1983-05-16 Hitachi Ltd 情報処理装置
DE3230836A1 (de) * 1982-08-19 1984-02-23 Standard Elektrik Lorenz Ag, 7000 Stuttgart Bi-phase-decoder
JPS59121697A (ja) * 1982-12-27 1984-07-13 Toshiba Corp シフトレジスタ
JPS60154709A (ja) * 1984-01-25 1985-08-14 Toshiba Corp クロツク信号発生回路
JPS60180216A (ja) * 1984-02-28 1985-09-14 Fujitsu Ltd 電圧検知回路
JPS60198618A (ja) * 1984-03-21 1985-10-08 Oki Electric Ind Co Ltd ダイナミツク論理回路
US4694196A (en) * 1984-12-07 1987-09-15 American Telephone And Telegraph Company And At&T Information Systems Clock recovery circuit
US4691122A (en) * 1985-03-29 1987-09-01 Advanced Micro Devices, Inc. CMOS D-type flip-flop circuits
US4700084A (en) * 1985-08-26 1987-10-13 Rockwell International Corporation Digital clock recovery circuit apparatus
JPH06101236B2 (ja) * 1985-10-25 1994-12-12 株式会社マイコンシステム シフトレジスタ
US4694197A (en) * 1986-01-06 1987-09-15 Rca Corporation Control signal generator

Also Published As

Publication number Publication date
US4736119A (en) 1988-04-05
CA1281088C (en) 1991-03-05
JPS63268312A (ja) 1988-11-07
HK117093A (en) 1993-11-05
EP0277767B1 (en) 1993-03-24
EP0277767A3 (en) 1989-10-04
DE3879524D1 (de) 1993-04-29
EP0277767A2 (en) 1988-08-10
DE3879524T2 (de) 1993-07-01
SG60193G (en) 1993-07-09
JPH073751B2 (ja) 1995-01-18

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