ES2047558T3 - Tecnica para ser utilizada en la fabricacion de dispositivos semiconductores que tienen caracteristicas submicrometricas. - Google Patents

Tecnica para ser utilizada en la fabricacion de dispositivos semiconductores que tienen caracteristicas submicrometricas.

Info

Publication number
ES2047558T3
ES2047558T3 ES88309484T ES88309484T ES2047558T3 ES 2047558 T3 ES2047558 T3 ES 2047558T3 ES 88309484 T ES88309484 T ES 88309484T ES 88309484 T ES88309484 T ES 88309484T ES 2047558 T3 ES2047558 T3 ES 2047558T3
Authority
ES
Spain
Prior art keywords
manufacture
opening
technique
submicrometric
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88309484T
Other languages
English (en)
Inventor
Anatoly Feygenson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of ES2047558T3 publication Critical patent/ES2047558T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

SE OBTIENE RESOLUCION SUBMICRO EN LA FABRICACION DE TRANSISTORES UTILIZANDO TECNICAS DE PARED LATERAL. EN LA TECNICA DESCRITA SE FORMA UNA ABERTURA CON UN ESPACIADOR DE PARED LATERAL DE NITRURO DE SILICIO EN UNA CAPA (9, 11). SE FORMA OXIDO (15) EN LA ABERTURA Y LUEGO EL ESPACIADOR DE PARED LATERAL SE ELIMINA PARA FORMAR UNA ABERTURA (17) ANULAR, QUE PUEDE SER DE UNA AMPLITUD PEQUEÑA Y CONTROLADA CON PRECISION. LUEGO LA ABERTURA SE USA COMO UNA DEFENSA PARA POSTERIOR MODIFICACION DEL SUBSTRATO POR DIFUSION O IMPLANTACION DE IONES.
ES88309484T 1987-10-20 1988-10-11 Tecnica para ser utilizada en la fabricacion de dispositivos semiconductores que tienen caracteristicas submicrometricas. Expired - Lifetime ES2047558T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/111,002 US4818713A (en) 1987-10-20 1987-10-20 Techniques useful in fabricating semiconductor devices having submicron features

Publications (1)

Publication Number Publication Date
ES2047558T3 true ES2047558T3 (es) 1994-03-01

Family

ID=22336098

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88309484T Expired - Lifetime ES2047558T3 (es) 1987-10-20 1988-10-11 Tecnica para ser utilizada en la fabricacion de dispositivos semiconductores que tienen caracteristicas submicrometricas.

Country Status (7)

Country Link
US (1) US4818713A (es)
EP (1) EP0313250B1 (es)
JP (1) JPH01124261A (es)
KR (1) KR910009033B1 (es)
CA (1) CA1299770C (es)
DE (1) DE3886672T2 (es)
ES (1) ES2047558T3 (es)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051805A (en) * 1987-07-15 1991-09-24 Rockwell International Corporation Sub-micron bipolar devices with sub-micron contacts
US5059544A (en) * 1988-07-14 1991-10-22 International Business Machines Corp. Method of forming bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy
JPH0744186B2 (ja) * 1989-03-13 1995-05-15 株式会社東芝 半導体装置の製造方法
US5227317A (en) * 1989-04-21 1993-07-13 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit bipolar transistor device
JPH02280340A (ja) * 1989-04-21 1990-11-16 Hitachi Ltd 半導体集積回路装置の製造方法
DE58909822D1 (de) * 1989-05-11 1997-11-27 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit einem lateralen Bipolartransistor
IT1231300B (it) * 1989-07-24 1991-11-28 Sgs Thomson Microelectronics Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore
US4902639A (en) * 1989-08-03 1990-02-20 Motorola, Inc. Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US4975385A (en) * 1990-04-06 1990-12-04 Applied Materials, Inc. Method of constructing lightly doped drain (LDD) integrated circuit structure
US5311054A (en) * 1991-03-25 1994-05-10 Harris Corporation Graded collector for inductive loads
EP0809279B1 (de) * 1991-09-23 2003-02-19 Infineon Technologies AG Verfahren zur Herstellung eines MOS-Transistors
KR100233832B1 (ko) * 1996-12-14 1999-12-01 정선종 반도체 소자의 트랜지스터 및 그 제조방법
DE102004034572B4 (de) 2004-07-17 2008-02-28 Infineon Technologies Ag Verfahren zum Herstellen einer Struktur auf der Oberfläche eines Substrats
US8083953B2 (en) 2007-03-06 2011-12-27 Micron Technology, Inc. Registered structure formation via the application of directed thermal energy to diblock copolymer films
US8557128B2 (en) 2007-03-22 2013-10-15 Micron Technology, Inc. Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
US8097175B2 (en) 2008-10-28 2012-01-17 Micron Technology, Inc. Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures, method for forming a metal oxide pattern, and method for patterning a semiconductor structure
US8372295B2 (en) 2007-04-20 2013-02-12 Micron Technology, Inc. Extensions of self-assembled structures to increased dimensions via a “bootstrap” self-templating method
US8404124B2 (en) 2007-06-12 2013-03-26 Micron Technology, Inc. Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces
US8080615B2 (en) 2007-06-19 2011-12-20 Micron Technology, Inc. Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide
US8999492B2 (en) 2008-02-05 2015-04-07 Micron Technology, Inc. Method to produce nanometer-sized features with directed assembly of block copolymers
US8425982B2 (en) 2008-03-21 2013-04-23 Micron Technology, Inc. Methods of improving long range order in self-assembly of block copolymer films with ionic liquids
US8426313B2 (en) 2008-03-21 2013-04-23 Micron Technology, Inc. Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference
US8114301B2 (en) 2008-05-02 2012-02-14 Micron Technology, Inc. Graphoepitaxial self-assembly of arrays of downward facing half-cylinders
US8900963B2 (en) 2011-11-02 2014-12-02 Micron Technology, Inc. Methods of forming semiconductor device structures, and related structures
US9087699B2 (en) 2012-10-05 2015-07-21 Micron Technology, Inc. Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device structure
US9229328B2 (en) 2013-05-02 2016-01-05 Micron Technology, Inc. Methods of forming semiconductor device structures, and related semiconductor device structures
US9177795B2 (en) 2013-09-27 2015-11-03 Micron Technology, Inc. Methods of forming nanostructures including metal oxides
TWI899456B (zh) * 2016-09-26 2025-10-01 日商力森諾科股份有限公司 樹脂組成物、半導體用配線層積層體及半導體裝置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538823B2 (es) * 1971-12-22 1980-10-07
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4236294A (en) * 1979-03-16 1980-12-02 International Business Machines Corporation High performance bipolar device and method for making same
US4272308A (en) * 1979-10-10 1981-06-09 Varshney Ramesh C Method of forming recessed isolation oxide layers
US4309812A (en) * 1980-03-03 1982-01-12 International Business Machines Corporation Process for fabricating improved bipolar transistor utilizing selective etching
US4338138A (en) * 1980-03-03 1982-07-06 International Business Machines Corporation Process for fabricating a bipolar transistor
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4640721A (en) * 1984-06-06 1987-02-03 Hitachi, Ltd. Method of forming bipolar transistors with graft base regions
EP0170250B1 (en) * 1984-07-31 1990-10-24 Kabushiki Kaisha Toshiba Bipolar transistor and method for producing the bipolar transistor
JPS6146063A (ja) * 1984-08-10 1986-03-06 Hitachi Ltd 半導体装置の製造方法
US4592792A (en) * 1985-01-23 1986-06-03 Rca Corporation Method for forming uniformly thick selective epitaxial silicon
US4698316A (en) * 1985-01-23 1987-10-06 Rca Corporation Method of depositing uniformly thick selective epitaxial silicon
US4641416A (en) * 1985-03-04 1987-02-10 Advanced Micro Devices, Inc. Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter
US4678537A (en) * 1985-05-23 1987-07-07 Sony Corporation Method of manufacturing semiconductor devices
US4728624A (en) * 1985-10-31 1988-03-01 International Business Machines Corporation Selective epitaxial growth structure and isolation
US4758530A (en) * 1986-12-08 1988-07-19 Delco Electronics Corporation Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
US4758531A (en) * 1987-10-23 1988-07-19 International Business Machines Corporation Method of making defect free silicon islands using SEG

Also Published As

Publication number Publication date
KR910009033B1 (ko) 1991-10-28
US4818713A (en) 1989-04-04
EP0313250B1 (en) 1993-12-29
EP0313250A3 (en) 1989-11-02
DE3886672D1 (de) 1994-02-10
EP0313250A2 (en) 1989-04-26
JPH01124261A (ja) 1989-05-17
DE3886672T2 (de) 1994-04-28
KR890007434A (ko) 1989-06-19
CA1299770C (en) 1992-04-28

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