IT1231300B - Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore - Google Patents

Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore

Info

Publication number
IT1231300B
IT1231300B IT8921281A IT2128189A IT1231300B IT 1231300 B IT1231300 B IT 1231300B IT 8921281 A IT8921281 A IT 8921281A IT 2128189 A IT2128189 A IT 2128189A IT 1231300 B IT1231300 B IT 1231300B
Authority
IT
Italy
Prior art keywords
realization
definition
layer
semiconductive material
reduced dimensions
Prior art date
Application number
IT8921281A
Other languages
English (en)
Other versions
IT8921281A0 (it
Inventor
Giuseppe Ferla
Paolo Lanza
Carmelo Magro
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8921281A priority Critical patent/IT1231300B/it
Publication of IT8921281A0 publication Critical patent/IT8921281A0/it
Priority to EP19900201927 priority patent/EP0410508A3/en
Priority to JP2193196A priority patent/JPH03141649A/ja
Priority to KR1019900011158A priority patent/KR910003750A/ko
Priority to US07/728,821 priority patent/US5130272A/en
Application granted granted Critical
Publication of IT1231300B publication Critical patent/IT1231300B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/111—Narrow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
IT8921281A 1989-07-24 1989-07-24 Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore IT1231300B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8921281A IT1231300B (it) 1989-07-24 1989-07-24 Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore
EP19900201927 EP0410508A3 (en) 1989-07-24 1990-07-14 Process for defining and forming an active region of very limited dimensions in a semiconductor layer
JP2193196A JPH03141649A (ja) 1989-07-24 1990-07-23 能動領域の形成方法
KR1019900011158A KR910003750A (ko) 1989-07-24 1990-07-23 초제한 크기의 활성 영역을 반도체층내에 정하여 형성하기 위한 방법
US07/728,821 US5130272A (en) 1989-07-24 1991-07-09 Process for defining and forming an active region of very limited dimensions in a semiconductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8921281A IT1231300B (it) 1989-07-24 1989-07-24 Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore

Publications (2)

Publication Number Publication Date
IT8921281A0 IT8921281A0 (it) 1989-07-24
IT1231300B true IT1231300B (it) 1991-11-28

Family

ID=11179486

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8921281A IT1231300B (it) 1989-07-24 1989-07-24 Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore

Country Status (5)

Country Link
US (1) US5130272A (it)
EP (1) EP0410508A3 (it)
JP (1) JPH03141649A (it)
KR (1) KR910003750A (it)
IT (1) IT1231300B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716859A (en) * 1995-12-22 1998-02-10 The Whitaker Corporation Method of fabricating a silicon BJT
US6214673B1 (en) * 1999-07-09 2001-04-10 Intersil Corporation Process for forming vertical semiconductor device having increased source contact area
US6090691A (en) * 1999-11-15 2000-07-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a raised source and drain without using selective epitaxial growth
US20040258977A1 (en) * 2003-01-24 2004-12-23 Hydrogenics Corporation Apparatus for and method of forming seals in fuel cells and fuel cell stacks

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3793721A (en) * 1971-08-02 1974-02-26 Texas Instruments Inc Integrated circuit and method of fabrication
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US4678537A (en) * 1985-05-23 1987-07-07 Sony Corporation Method of manufacturing semiconductor devices
DE3688057T2 (de) * 1986-01-10 1993-10-07 Gen Electric Halbleitervorrichtung und Methode zur Herstellung.
IT1204243B (it) * 1986-03-06 1989-03-01 Sgs Microelettronica Spa Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento
US4716126A (en) * 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
JPH0834311B2 (ja) * 1987-06-10 1996-03-29 日本電装株式会社 半導体装置の製造方法
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
US4960723A (en) * 1989-03-30 1990-10-02 Motorola, Inc. Process for making a self aligned vertical field effect transistor having an improved source contact

Also Published As

Publication number Publication date
IT8921281A0 (it) 1989-07-24
JPH03141649A (ja) 1991-06-17
EP0410508A2 (en) 1991-01-30
KR910003750A (ko) 1991-02-28
US5130272A (en) 1992-07-14
EP0410508A3 (en) 1991-11-27

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730