ES2060351T3 - Procedimiento y dispositivo para la recuperacion del impulso de reloj. - Google Patents

Procedimiento y dispositivo para la recuperacion del impulso de reloj.

Info

Publication number
ES2060351T3
ES2060351T3 ES91900788T ES91900788T ES2060351T3 ES 2060351 T3 ES2060351 T3 ES 2060351T3 ES 91900788 T ES91900788 T ES 91900788T ES 91900788 T ES91900788 T ES 91900788T ES 2060351 T3 ES2060351 T3 ES 2060351T3
Authority
ES
Spain
Prior art keywords
correction value
stop
output
phase
impulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91900788T
Other languages
English (en)
Inventor
Wilhelm Volejnik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2060351T3 publication Critical patent/ES2060351T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Structures Of Non-Positive Displacement Pumps (AREA)
  • Jet Pumps And Other Pumps (AREA)

Abstract

EN LA PARADA DEL MODO BYTE DE UNA SEÑAL SINCRONA EN UNA JERARQUIA MULTIPLEX DIGITAL SINCRONA, APARECE UN JITTER CON SALTO DE FASE DE 8 UI QUE OFRECE DIFICULTAD DE RECUPERACION DEL IMPULSO. SE BUSCA POR TANTO UNA POSIBILIDAD DE TRANSFORMAR JITTER EN IMPULSO. ESTO SE CONSIGUE CON UN LAZO (PLL) REGULADOR DE FASE EN EL QUE UN COMPENSADOR (7) DE SALTO DE FASE ESTA INSERTADO ENTRE LA SALIDA (4) DE UN DISCRIMINADOR (3) DE FASE Y LA SALIDA (5) DE UN OSCILADOR (6). ESTO CONVIERTE UN VALOR (KE) DE CORRECCION DE ENTRADA EN UN VALOR (KA) DE CORRECCION DE SALIDA. SI NO SE PRODUCE UNA PARADA, EL VALOR (KE) DE CORRECCION DE ENTRADA DEJA EL COMPENSADOR (7) DE SALTO DE FASE INALTERADO (A1, B1). SI SE PRODUCE UNA PARADA POSITIVA (+ST), LOS IMPULSOS DEL VALOR (KE) DE CORRECCION DE ENTRADA ALARGADOS SE ACORTAN PRIMERO A LA DURACION NORMAL (X1) Y ENTONCES SE ALARGAN DE FORMA ESCALONADA (CL,DL) A LA DURACION ORIGINAL. EN PARADA NEGATIVA (-ST) LOS IMPULSOS ACORTADOS DE UN VALOR (KE) DE CORRECCION DE ENTRADA SON PRIMERO ALARGADOS A LA DURACION NORMAL Y ENTONCES ACORTADOS DE FORMA ESCALONADA EN ETAPAS (EL, FL).
ES91900788T 1990-02-16 1990-12-04 Procedimiento y dispositivo para la recuperacion del impulso de reloj. Expired - Lifetime ES2060351T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP90103071 1990-02-16

Publications (1)

Publication Number Publication Date
ES2060351T3 true ES2060351T3 (es) 1994-11-16

Family

ID=8203662

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91900788T Expired - Lifetime ES2060351T3 (es) 1990-02-16 1990-12-04 Procedimiento y dispositivo para la recuperacion del impulso de reloj.

Country Status (14)

Country Link
US (1) US5426672A (es)
EP (1) EP0515376B1 (es)
JP (1) JPH05504240A (es)
AR (1) AR245548A1 (es)
AT (1) ATE110205T1 (es)
AU (1) AU642948B2 (es)
BR (1) BR9007998A (es)
CA (1) CA2076039C (es)
DE (1) DE59006856D1 (es)
DK (1) DK0515376T3 (es)
ES (1) ES2060351T3 (es)
FI (1) FI923638A7 (es)
NO (1) NO923190D0 (es)
WO (1) WO1991012678A1 (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268935A (en) * 1991-12-20 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
FI90709C (fi) * 1992-02-14 1994-03-10 Nokia Telecommunications Oy Järjestely osoitinvärinän vaimentamiseksi desynkronisaattorissa
FI95636C (fi) 1992-02-14 1996-02-26 Nokia Telecommunications Oy Desynkronisaattori ja menetelmä osoitinvärinän vaimentamiseksi desynkronisaattorissa
JPH07245603A (ja) * 1994-01-11 1995-09-19 Fujitsu Ltd ジッタ抑圧制御方法およびその回路
DE4412060C1 (de) * 1994-04-07 1995-02-23 Siemens Ag Anordnung zur Rückgewinnung eines plesiochronen Digitalsignals
GB9509216D0 (en) * 1995-05-05 1995-06-28 Plessey Telecomm Retiming arrangement for SDH data transmission system
DE19653470C2 (de) * 1996-12-20 1998-10-08 Siemens Ag Verfahren und Anordnung zur Taktrückgewinnung aus einem Digitalsignal
DE60206468T2 (de) * 2002-02-28 2006-05-11 Alcatel Plesiochroner Demultiplexer
AU2003244972A1 (en) * 2002-06-25 2004-01-06 Koninklijke Philips Electronics N.V. Clock recovery for a dvb-t to dvb-s transmodulator
RU2233039C1 (ru) * 2003-02-25 2004-07-20 Военный университет связи Способ синхронизации сети связи
US7243169B2 (en) * 2004-06-08 2007-07-10 International Business Machines Corporation Method, system and program for oscillation control of an internal process of a computer program
RU2321167C2 (ru) * 2006-01-13 2008-03-27 Самсунг Электроникс Ко., Лтд. Способ компенсации скачков опорного сигнала фазовой автоподстройки частоты

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1762746A1 (de) * 1967-08-21 1970-08-20 Synchron Druzstov Pro Vyvoj A Verfahren zur Syntonisation genauer Oszillatoren und Anordnung zum Durchfuehren dieses Verfahrens
CH536046A (de) * 1967-08-21 1973-04-15 Synchron Druzstvo Pro Vyvoj Ku Verfahren zur automatischen Regelung von Oszillatoren und Anordnung zum Durchführen dieses Verfahrens
US4019143A (en) * 1976-05-10 1977-04-19 Bell Telephone Laboratories, Incorporated Standby apparatus for clock signal generators
DE3202540A1 (de) * 1982-01-27 1983-08-04 AEG-Telefunken Nachrichtentechnik GmbH, 7150 Backnang Verfahren und anordnung zur taktsynchronisierung auf der empfangsseite eines plesiochronen uebertragungssytems
US4563657A (en) * 1982-03-15 1986-01-07 Codex Corporation Frequency synthesizer and digital phase lock loop
US4610259A (en) * 1983-08-31 1986-09-09 Cns, Inc. EEG signal analysis system
US4709170A (en) * 1984-08-20 1987-11-24 National Semiconductor Corp. Subnanosecond programmable phase shifter for a high frequency digital PLL
US4608702A (en) * 1984-12-21 1986-08-26 Advanced Micro Devices, Inc. Method for digital clock recovery from Manchester-encoded signals
US4803680A (en) * 1985-12-27 1989-02-07 Nec Corporation Destuffing circuit with a digital phase-locked loop
FR2601534B1 (fr) * 1986-07-10 1993-07-30 Cit Alcatel Procede et dispositif de calage en phase de trains numeriques synchrones
US5146477A (en) * 1987-03-17 1992-09-08 Antonio Cantoni Jitter control in digital communication links
US4941156A (en) * 1987-05-19 1990-07-10 Crystal Semiconductor Linear jitter attenuator
AR241983A1 (es) * 1989-03-23 1993-01-29 Siemens Ag Disposicion de circuito para transformar una secuencia discontinua de pulsos de reloj de entrada en una secuencia continua de pulsos de reloj de salida con la misma cantidad de pulsos.
US5131013A (en) * 1990-05-30 1992-07-14 At&T Bell Laboratories Asynchronous-synchronous digital transmission signal conversion

Also Published As

Publication number Publication date
CA2076039C (en) 2001-01-30
DE59006856D1 (de) 1994-09-22
CA2076039A1 (en) 1991-08-17
EP0515376A1 (de) 1992-12-02
US5426672A (en) 1995-06-20
FI923638A0 (fi) 1992-08-14
AU6917091A (en) 1991-09-03
FI923638A7 (fi) 1992-08-14
NO923190L (no) 1992-08-14
BR9007998A (pt) 1992-10-27
AU642948B2 (en) 1993-11-04
AR245548A1 (es) 1994-01-31
JPH05504240A (ja) 1993-07-01
NO923190D0 (no) 1992-08-14
DK0515376T3 (da) 1994-11-14
EP0515376B1 (de) 1994-08-17
WO1991012678A1 (de) 1991-08-22
ATE110205T1 (de) 1994-09-15

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