ES2069858T3 - Modulos de memoria en estado solido y dispositivos de memoria que comprenden dichos modulos. - Google Patents

Modulos de memoria en estado solido y dispositivos de memoria que comprenden dichos modulos.

Info

Publication number
ES2069858T3
ES2069858T3 ES91403267T ES91403267T ES2069858T3 ES 2069858 T3 ES2069858 T3 ES 2069858T3 ES 91403267 T ES91403267 T ES 91403267T ES 91403267 T ES91403267 T ES 91403267T ES 2069858 T3 ES2069858 T3 ES 2069858T3
Authority
ES
Spain
Prior art keywords
modules
memory
solid state
memory devices
state memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91403267T
Other languages
English (en)
Inventor
Givry Jacques De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Matra Marconi Space France SA
Original Assignee
Matra Marconi Space France SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matra Marconi Space France SA filed Critical Matra Marconi Space France SA
Application granted granted Critical
Publication of ES2069858T3 publication Critical patent/ES2069858T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Combinations Of Printed Boards (AREA)
  • Dram (AREA)

Abstract

MODULO DE MEMORIA QUE COMPRENDE SOBRE UN SUSTRATO (12) DE INTERCONEXION, VARIAS PULGAS DE MEMORIA DE SEMICONDUCTORES DE FORMA ALARGADA CUYAS SALIDAS ESTAN LOCALIZADAS EN LOS EXTREMOS. COMPRENDE AL MENOS DOS PULGAS (14, 16) APILADAS Y CRUZADAS.
ES91403267T 1990-12-05 1991-12-03 Modulos de memoria en estado solido y dispositivos de memoria que comprenden dichos modulos. Expired - Lifetime ES2069858T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9015210A FR2670322B1 (fr) 1990-12-05 1990-12-05 Modules de memoire a l'etat solide et dispositifs de memoire comportant de tels modules

Publications (1)

Publication Number Publication Date
ES2069858T3 true ES2069858T3 (es) 1995-05-16

Family

ID=9402909

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91403267T Expired - Lifetime ES2069858T3 (es) 1990-12-05 1991-12-03 Modulos de memoria en estado solido y dispositivos de memoria que comprenden dichos modulos.

Country Status (6)

Country Link
US (1) US5229960A (es)
EP (1) EP0489643B1 (es)
JP (1) JPH05121643A (es)
DE (1) DE69107808T2 (es)
ES (1) ES2069858T3 (es)
FR (1) FR2670322B1 (es)

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US7053476B2 (en) * 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
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US7064426B2 (en) * 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US7034387B2 (en) * 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
TWI322448B (en) * 2002-10-08 2010-03-21 Chippac Inc Semiconductor stacked multi-package module having inverted second package
JP3776427B2 (ja) * 2003-11-17 2006-05-17 沖電気工業株式会社 半導体装置及びその製造方法
US8970049B2 (en) * 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
TWI233170B (en) * 2004-02-05 2005-05-21 United Microelectronics Corp Ultra-thin wafer level stack packaging method and structure using thereof
JP4538830B2 (ja) 2004-03-30 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置
US20050258527A1 (en) * 2004-05-24 2005-11-24 Chippac, Inc. Adhesive/spacer island structure for multiple die package
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US7863720B2 (en) 2004-05-24 2011-01-04 Honeywell International Inc. Method and system for stacking integrated circuits
US8552551B2 (en) * 2004-05-24 2013-10-08 Chippac, Inc. Adhesive/spacer island structure for stacking over wire bonded die
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US7253511B2 (en) * 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
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US7492039B2 (en) 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
TWI442520B (zh) * 2005-03-31 2014-06-21 史達特司奇帕克有限公司 具有晶片尺寸型封裝及第二基底及在上側與下側包含暴露基底表面之半導體組件
WO2006105514A2 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US7364945B2 (en) * 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7429786B2 (en) * 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7582960B2 (en) * 2005-05-05 2009-09-01 Stats Chippac Ltd. Multiple chip package module including die stacked over encapsulated package
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US8026611B2 (en) 2005-12-01 2011-09-27 Tessera, Inc. Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another
US7342308B2 (en) * 2005-12-20 2008-03-11 Atmel Corporation Component stacking for integrated circuit electronic package
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
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US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) * 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US20070279079A1 (en) * 2006-05-31 2007-12-06 Jianxiang Chang Multiple chip package test program and programming architecture
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US20090127694A1 (en) * 2007-11-14 2009-05-21 Satoshi Noro Semiconductor module and image pickup apparatus
JP5105417B2 (ja) * 2007-11-20 2012-12-26 スパンション エルエルシー 半導体装置及びその製造方法
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KR102062738B1 (ko) * 2013-02-25 2020-01-06 삼성전자주식회사 반도체 패키지
JP7226358B2 (ja) * 2020-02-05 2023-02-21 株式会社デンソー 電子機器

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Also Published As

Publication number Publication date
EP0489643B1 (fr) 1995-03-01
JPH05121643A (ja) 1993-05-18
US5229960A (en) 1993-07-20
FR2670322B1 (fr) 1997-07-04
DE69107808D1 (de) 1995-04-06
FR2670322A1 (fr) 1992-06-12
DE69107808T2 (de) 1995-06-29
EP0489643A1 (fr) 1992-06-10

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