ES2076249T3 - Procedimiento para ensayar una unidad direccionable minima de una ram con respecto a errores binarios que existen por encima de un numero determinado. - Google Patents
Procedimiento para ensayar una unidad direccionable minima de una ram con respecto a errores binarios que existen por encima de un numero determinado.Info
- Publication number
- ES2076249T3 ES2076249T3 ES90108057T ES90108057T ES2076249T3 ES 2076249 T3 ES2076249 T3 ES 2076249T3 ES 90108057 T ES90108057 T ES 90108057T ES 90108057 T ES90108057 T ES 90108057T ES 2076249 T3 ES2076249 T3 ES 2076249T3
- Authority
- ES
- Spain
- Prior art keywords
- testing
- ram
- procedure
- respect
- addressable unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Error Detection And Correction (AREA)
- Communication Control (AREA)
- Time-Division Multiplex Systems (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
EL TEST DE UNA DE LAS UNIDADES MAS PEQUEÑA DIRECCIONABLES DE UN MEDIO DE MEMORIA, DEBE TENER LUGAR DE FORMA COMPLETA Y AL MISMO TIEMPO. POR ESTE MOTIVO SE EMPLEA UN PROCESO DE TEST BASADO EN LA FORMACION PARITARIA CON AL MENOS DOS MUESTRA DE TEST, DONDE EN LA PRIMERA MUESTRA DE TEST EL FALLO DE BIT RECONOCEDOR SE TRANSMITE A LA SIGUIENTE MUESTRA DE TEST Y EN LA TRANSMISION DE ESTA MUESTRA DE TEST SE RECONOCE EL FALLO DEL BIT QUE DA LA ADICCION DEL PRIMERO Y LA SEGUNDA MUESTRA DE TEST DA COMO RESULTADO LOS FALLOS DE BIT SEPARADOS APARECIDOS.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP90108057A EP0453609B1 (de) | 1990-04-27 | 1990-04-27 | Verfahren zum Testen einer kleinsten adressierbaren Einheit eines RAM's auf über einer bestimmten Zahl liegende Bitfehler |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2076249T3 true ES2076249T3 (es) | 1995-11-01 |
Family
ID=8203924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES90108057T Expired - Lifetime ES2076249T3 (es) | 1990-04-27 | 1990-04-27 | Procedimiento para ensayar una unidad direccionable minima de una ram con respecto a errores binarios que existen por encima de un numero determinado. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5293383A (es) |
| EP (1) | EP0453609B1 (es) |
| AT (1) | ATE127597T1 (es) |
| DE (1) | DE59009636D1 (es) |
| ES (1) | ES2076249T3 (es) |
| GR (1) | GR3017394T3 (es) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5502732A (en) * | 1993-09-20 | 1996-03-26 | International Business Machines Corporation | Method for testing ECC logic |
| US5511164A (en) | 1995-03-01 | 1996-04-23 | Unisys Corporation | Method and apparatus for determining the source and nature of an error within a computer system |
| US6105156A (en) * | 1996-01-23 | 2000-08-15 | Nec Corporation | LSI tester for use in LSI fault analysis |
| US6286116B1 (en) * | 1999-03-26 | 2001-09-04 | Compaq Computer Corporation | Built-in test method for content addressable memories |
| US6879530B2 (en) * | 2002-07-18 | 2005-04-12 | Micron Technology, Inc. | Apparatus for dynamically repairing a semiconductor memory |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5381036A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Error correction-detection system |
| US4251863A (en) * | 1979-03-15 | 1981-02-17 | Sperry Corporation | Apparatus for correction of memory errors |
| DE3482509D1 (de) * | 1984-12-28 | 1990-07-19 | Ibm | Geraet zum korrigieren von fehlern in speichern. |
| US4782487A (en) * | 1987-05-15 | 1988-11-01 | Digital Equipment Corporation | Memory test method and apparatus |
| US4980888A (en) * | 1988-09-12 | 1990-12-25 | Digital Equipment Corporation | Memory testing system |
-
1990
- 1990-04-27 DE DE59009636T patent/DE59009636D1/de not_active Expired - Fee Related
- 1990-04-27 EP EP90108057A patent/EP0453609B1/de not_active Expired - Lifetime
- 1990-04-27 ES ES90108057T patent/ES2076249T3/es not_active Expired - Lifetime
- 1990-04-27 AT AT90108057T patent/ATE127597T1/de not_active IP Right Cessation
-
1991
- 1991-04-15 US US07/684,836 patent/US5293383A/en not_active Expired - Fee Related
-
1995
- 1995-09-13 GR GR950402519T patent/GR3017394T3/el unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP0453609A1 (de) | 1991-10-30 |
| EP0453609B1 (de) | 1995-09-06 |
| GR3017394T3 (en) | 1995-12-31 |
| DE59009636D1 (de) | 1995-10-12 |
| US5293383A (en) | 1994-03-08 |
| ATE127597T1 (de) | 1995-09-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG2A | Definitive protection |
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