ES2079367T3 - Metodo y aparato para la recuperacion de fallos en un sistema de ordenadores digitales. - Google Patents

Metodo y aparato para la recuperacion de fallos en un sistema de ordenadores digitales.

Info

Publication number
ES2079367T3
ES2079367T3 ES89118684T ES89118684T ES2079367T3 ES 2079367 T3 ES2079367 T3 ES 2079367T3 ES 89118684 T ES89118684 T ES 89118684T ES 89118684 T ES89118684 T ES 89118684T ES 2079367 T3 ES2079367 T3 ES 2079367T3
Authority
ES
Spain
Prior art keywords
memory
cpu
series
bits
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89118684T
Other languages
English (en)
Inventor
Richard F Hess
Kurt A Liebel
Larry J Yount
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Application granted granted Critical
Publication of ES2079367T3 publication Critical patent/ES2079367T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

UN METODO Y UN APARATO PARA RECUPERAR FALLOS EN UN SISTEMA DE CONTROL QUE TIENE POR BASE UN COMPUTADOR DIGITAL POR EL CUAL PUEDEN RECUPERARSE LAS ALTERACIONES DEL SISTEMA PRODUCIDAS POR CONDICIONES DE RUIDOS TRANSITORIOS EXTERIORES. SE ACOPLA UNA CPU (10) A SU MEMEORIA PRINCIPAL (20) Y A SU INTERFACE DE E/S (ENTRADA / SALIDA) MEDIANTE UN COLECTOR DE DIRECCIONAMIENTO/DATOS (22) COMUN, PUDIENDOSE ALTERAR LOS DATOS CONTENIDOS SOBRE O EN ESTOS TRES ELEMENTOS POR EL EFECTO DE RUIDOS TRANSITORIOS. TAMBIEN ACOPLADOS AL COLECTOR, PERO EN UN MEDIO DE HARDWARE, EXISTEN PRIMERAS Y SEGUNDAS MEMORIAS SUPLEMENTARIAS (34, 36) QUE, POR CONTROL DE LA MEMORIA (38), OPERAN PARA ALTERNAR LAS SERIES DE BITS DE CALCULO PARES E IMPARES DEFINIDAS POR EL RELOJ DE TIEMPO REAL DE LA CPU PARA ALMACENAR LAS MISMAS PALABRAS QUE SE INCORPOREN EN ESE MOMENTO EN LA MEMORIA PRINCIPAL (20) DE LA CPU. A MEDIDA QUE ESTAS SERIES DE BITS DE CALCULO ENTRAN EN UNA U OTRA DE ESTAS DOS MEMORIAS (34, 36) POR INTRODUCCION NO AUTORIZADA EN EL COLECTOR COMUN (22), LA OTRA MEMORIA SUPLEMENTARIA TRANSFIERE SUS CONTENIDOS A UNA MEMORIA AUXILIAR (30) QUE TAMBIEN SE UBICA EN EL MEDIO INMUNE AL RUIDO. SE CONECTA LA MEMORIA AUXILIAR EN UNA MODALIDAD DE SOLO LECTURA AL COLECTOR DE DIRECCIONAMIENTO/DATOS Y, DEBIDO A SU FORMA DE OPERACION, SIEMPRE CONTIENE LA SERIE DE BITS RETRASADA EN UN CICLO DEL RELOJ DE TIEMPO REAL DE LA CPU CON RESPECTO A LA SERIE DE BITS EN PROCESO. SI SE ALTERARA UN TRANSITORIO, PODRIA CONTINUAR UNA TRANSFERENCIA DE INFORMACION DESDE LA MEMORIA AUXILIAR (30) A LA MEMORIA PRINCIPAL (20) DEL ORDENADOR, DE MANERA QUE LOS CALCULOS PUEDAN CONTINUAR CON LOS DATOS NO ALTERADOS.
ES89118684T 1988-10-11 1989-10-07 Metodo y aparato para la recuperacion de fallos en un sistema de ordenadores digitales. Expired - Lifetime ES2079367T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/256,060 US4996687A (en) 1988-10-11 1988-10-11 Fault recovery mechanism, transparent to digital system function

Publications (1)

Publication Number Publication Date
ES2079367T3 true ES2079367T3 (es) 1996-01-16

Family

ID=22970958

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89118684T Expired - Lifetime ES2079367T3 (es) 1988-10-11 1989-10-07 Metodo y aparato para la recuperacion de fallos en un sistema de ordenadores digitales.

Country Status (6)

Country Link
US (1) US4996687A (es)
EP (1) EP0363863B1 (es)
JP (1) JP2791697B2 (es)
CA (1) CA1322606C (es)
DE (1) DE68924119T2 (es)
ES (1) ES2079367T3 (es)

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US9430494B2 (en) * 2009-12-28 2016-08-30 Oracle International Corporation Spatial data cartridge for event processing systems
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Also Published As

Publication number Publication date
DE68924119T2 (de) 1996-07-04
EP0363863A2 (en) 1990-04-18
EP0363863B1 (en) 1995-09-06
EP0363863A3 (en) 1991-07-03
CA1322606C (en) 1993-09-28
US4996687A (en) 1991-02-26
JPH02253344A (ja) 1990-10-12
JP2791697B2 (ja) 1998-08-27
DE68924119D1 (de) 1995-10-12

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