ES2080805T3 - Metodo y aparato para generar señales de control. - Google Patents

Metodo y aparato para generar señales de control.

Info

Publication number
ES2080805T3
ES2080805T3 ES90309074T ES90309074T ES2080805T3 ES 2080805 T3 ES2080805 T3 ES 2080805T3 ES 90309074 T ES90309074 T ES 90309074T ES 90309074 T ES90309074 T ES 90309074T ES 2080805 T3 ES2080805 T3 ES 2080805T3
Authority
ES
Spain
Prior art keywords
macro
register
control
bit
identity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90309074T
Other languages
English (en)
Inventor
Najmi T Jarwala
Chi W Yau
Paul W Rutkowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2080805T3 publication Critical patent/ES2080805T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318561—Identification of the subpart
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Selective Calling Equipment (AREA)
  • Control Of Eletrric Generators (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Debugging And Monitoring (AREA)

Abstract

SE DIFUNDE UN METODO PARA GENERACION DE UNA SEÑAL DE CONTROL (TMS) QUE SE PUEDE USAR PARA CONTROLAR LA ACTIVIDAD DE PRUEBA DE UN SISTEMA DE EXPLORACION DE LIMITES (10). EL METODO SE INICIA CARGANDO UNA MACROINSTRUCCION DE CONTROL MULTI-BIT (STI,DTI O DSTI) EN UN REGISTRO (38) CUYA SALIDA SE ACOPLA EN EL RETORNO A SU ENTRADA. DESPUES DE LA CARGA DE LA MACROINSTRUCCION, SE ADIVINA SU IDENTIDAD MEDIANTE UN CONTROLADOR MACRO (42) QUE SIRVE PARA DECODIFICAR UNA SEÑAL MULTI-BIT (IT) CUYO ESTADO ES INDICATIVO DEL TIPO DE MACRO. EL CONTROLADOR MACRO (42) ACTUA EL REGISTRO PARA DESPLAZAMIENTO DE LOS BIT DE CONTROL MACRO EN UNA SECUENCIA DEPENDIENTE DE LA IDENTIDAD DE LA MACRO AL OBJETO DE GENERAR LA SEÑAL DE CONTROL APROPIADA. SEGUN SE DESPLAZA CADA UNO DE LOS BIT, SE DESPLAZAN DE RETORNO DENTRO DEL REGISTRO, PARA PERMITIR QUE LA MISMA SECUENCIA DE BIT SE DESPLACE REPETIDAMENTE.
ES90309074T 1989-08-28 1990-08-17 Metodo y aparato para generar señales de control. Expired - Lifetime ES2080805T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/399,132 US5048021A (en) 1989-08-28 1989-08-28 Method and apparatus for generating control signals

Publications (1)

Publication Number Publication Date
ES2080805T3 true ES2080805T3 (es) 1996-02-16

Family

ID=23578280

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90309074T Expired - Lifetime ES2080805T3 (es) 1989-08-28 1990-08-17 Metodo y aparato para generar señales de control.

Country Status (7)

Country Link
US (1) US5048021A (es)
EP (1) EP0415614B1 (es)
JP (1) JPH0396881A (es)
KR (1) KR0180002B1 (es)
AT (1) ATE131639T1 (es)
DE (1) DE69024138T2 (es)
ES (1) ES2080805T3 (es)

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Publication number Priority date Publication date Assignee Title
US5353308A (en) * 1990-08-06 1994-10-04 Texas Instruments Incorporated Event qualified test methods and circuitry
KR100217535B1 (ko) * 1990-08-06 1999-09-01 윌리엄 비. 켐플러 이벤트 한정 검사 아키텍춰
US5228045A (en) * 1990-08-06 1993-07-13 Ncr Corporation Test driver for connecting a standard test port integrated circuit chip to a controlling computer
FR2670299B1 (fr) * 1990-12-07 1993-01-22 Thomson Composants Militaires Circuit integre avec controleur de test peripherique.
US5313470A (en) * 1991-09-17 1994-05-17 Ncr Corporation Boundary-scan input cell for a clock pin
JP2973641B2 (ja) * 1991-10-02 1999-11-08 日本電気株式会社 Ｔａｐコントローラ
US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
US5485466A (en) * 1993-10-04 1996-01-16 Motorola, Inc. Method and apparatus for performing dual scan path testing of an array in a data processing system
US5717702A (en) * 1995-03-14 1998-02-10 Hughes Electronics Scan testing digital logic with differing frequencies of system clock and test clock
DE69606129T3 (de) * 1995-10-13 2015-03-05 Jtag Technologies B.V. Verfahren und Tester zur Beaufschlagung eines elektronischen Bausteins mit einem Triggerimpuls
US5719879A (en) * 1995-12-21 1998-02-17 International Business Machines Corporation Scan-bypass architecture without additional external latches
US6028983A (en) * 1996-09-19 2000-02-22 International Business Machines Corporation Apparatus and methods for testing a microprocessor chip using dedicated scan strings
US5900753A (en) * 1997-03-28 1999-05-04 Logicvision, Inc. Asynchronous interface
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6594802B1 (en) * 2000-03-23 2003-07-15 Intellitech Corporation Method and apparatus for providing optimized access to circuits for debug, programming, and test
US6785854B1 (en) * 2000-10-02 2004-08-31 Koninklijke Philips Electronics N.V. Test access port (TAP) controller system and method to debug internal intermediate scan test faults
US6925583B1 (en) * 2002-01-09 2005-08-02 Xilinx, Inc. Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device
US7131033B1 (en) * 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US7689866B2 (en) 2006-10-18 2010-03-30 Alcatel-Lucent Usa Inc. Method and apparatus for injecting transient hardware faults for software testing
US8037355B2 (en) * 2007-06-07 2011-10-11 Texas Instruments Incorporated Powering up adapter and scan test logic TAP controllers
US7685484B2 (en) * 2007-11-14 2010-03-23 International Business Machines Corporation Methods for the support of JTAG for source synchronous interfaces
CN109633420A (zh) * 2018-12-23 2019-04-16 中国航空工业集团公司洛阳电光设备研究所 一种探针式故障注入板卡

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2256706A5 (es) * 1973-12-27 1975-07-25 Cii
DE3009945C2 (de) * 1979-03-15 1987-03-19 Nippon Electric Co., Ltd., Tokio/Tokyo Funktionsprüfbarer, integrierter Schaltkreis
US4361896A (en) * 1979-09-12 1982-11-30 General Electric Company Binary detecting and threshold circuit
US4729093A (en) * 1984-09-26 1988-03-01 Motorola, Inc. Microcomputer which prioritizes instruction prefetch requests and data operand requests
US4774681A (en) * 1985-03-11 1988-09-27 Tektronix, Inc. Method and apparatus for providing a histogram
US4785410A (en) * 1985-06-05 1988-11-15 Clarion Co., Ltd. Maximum length shift register sequences generator
JP2610417B2 (ja) * 1985-12-23 1997-05-14 日本テキサス・インスツルメンツ株式会社 アドレス信号生成方法及びその回路
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
NL192801C (nl) * 1986-09-10 1998-02-03 Philips Electronics Nv Werkwijze voor het testen van een drager met meerdere digitaal-werkende geïntegreerde schakelingen, geïntegreerde schakeling geschikt voor het aanbrengen op een aldus te testen drager, en drager voorzien van meerdere van zulke geïntegreerde schakelingen.
JP2556017B2 (ja) * 1987-01-17 1996-11-20 日本電気株式会社 論理集積回路
JP2594130B2 (ja) * 1988-09-02 1997-03-26 三菱電機株式会社 半導体回路
US4965800A (en) * 1988-10-11 1990-10-23 Farnbach William A Digital signal fault detector

Also Published As

Publication number Publication date
EP0415614B1 (en) 1995-12-13
DE69024138D1 (de) 1996-01-25
EP0415614A2 (en) 1991-03-06
EP0415614A3 (en) 1992-04-08
ATE131639T1 (de) 1995-12-15
US5048021A (en) 1991-09-10
KR910005064A (ko) 1991-03-29
JPH0396881A (ja) 1991-04-22
DE69024138T2 (de) 1996-05-09
KR0180002B1 (ko) 1999-04-01

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