ES2082765T3 - Circuito de interfaz de lineas. - Google Patents
Circuito de interfaz de lineas.Info
- Publication number
- ES2082765T3 ES2082765T3 ES89120157T ES89120157T ES2082765T3 ES 2082765 T3 ES2082765 T3 ES 2082765T3 ES 89120157 T ES89120157 T ES 89120157T ES 89120157 T ES89120157 T ES 89120157T ES 2082765 T3 ES2082765 T3 ES 2082765T3
- Authority
- ES
- Spain
- Prior art keywords
- line
- attenuation
- interface circuit
- line interface
- binary data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/12—Compensating for variations in line impedance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Networks Using Active Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Details Of Aerials (AREA)
- Electric Cable Installation (AREA)
- Glass Compositions (AREA)
- Amplifiers (AREA)
Abstract
EN UN CIRCUITO DE INTERFAZ DE LINEA PARA SEÑALES DE DATOS BINARIOS SE PROVEE MEDIOS PARA COMPENSAR LAS DISTINTAS LONGITUDES DE LINEA EN EL TRAYECTO DE RECEPCION Y/O TRANSMISION. LA SEÑAL DE UN ECUALIZADOR DE LINEA CONTROLA UN CIRCUITO DE IMPEDANCIA VARIABLE DE TAL MANERA QUE LA ATENUACION DE UNA RED DE ELABORACION DE LINEA SE REDUCE SI EL NIVEL DE SALIDA DEL ECUALIZADOR DESCIENDE POR DEBAJO DE UN CIERTO UMBRAL. UNA RED DE ELABORACION DE LINEA DE TRANSMISION PROVEE UNA FRECUENCIA QUE DEPENDE DE LA ATENUACION DE LOS DATOS BINARIOS POR MEDIO DE UN CIRCUITO DE CONTROL, QUE SUMINISTRA VALORES DE ATENUACION DISCRETOS DE ACUERDO CON UNA PALABRA LOGICA.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/266,082 US4964116A (en) | 1988-11-02 | 1988-11-02 | DS3 - line interface linear array (lila) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2082765T3 true ES2082765T3 (es) | 1996-04-01 |
Family
ID=23013099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES89120157T Expired - Lifetime ES2082765T3 (es) | 1988-11-02 | 1989-10-31 | Circuito de interfaz de lineas. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4964116A (es) |
| EP (1) | EP0367208B1 (es) |
| AT (1) | ATE133525T1 (es) |
| CA (1) | CA1337078C (es) |
| DE (1) | DE68925514T2 (es) |
| ES (1) | ES2082765T3 (es) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6782096B1 (en) * | 1998-11-12 | 2004-08-24 | Paradyne Corporation | Subscriber line driver and termination |
| US6975694B1 (en) * | 1999-12-15 | 2005-12-13 | Paradyne Corporation | Digital subscriber line driver |
| US20040151237A1 (en) * | 2000-05-31 | 2004-08-05 | Bitrage, Inc. | Satellite communications system |
| US6823001B1 (en) | 2000-05-31 | 2004-11-23 | Bitrage, Inc. | Dual stage communication processor |
| US7149242B1 (en) | 2000-05-31 | 2006-12-12 | Bitrage, Inc. | Communications system for improving transmission rates and transmission distances of data signals across communications links |
| US7356555B2 (en) | 2002-03-29 | 2008-04-08 | Intel Corporation | In-protocol impedance compensation control |
| US7135925B2 (en) * | 2004-12-03 | 2006-11-14 | Rambus Inc. | Adaptive bias scheme for high-voltage compliance in serial links |
| US20070076132A1 (en) * | 2005-10-05 | 2007-04-05 | Sure-Fire Electrical Corporation | [signal adjuster] |
| US7642853B2 (en) * | 2007-08-23 | 2010-01-05 | Qualcomm, Incorporated | High-swing operational amplifier output stage using adaptive biasing |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3568100A (en) * | 1967-12-26 | 1971-03-02 | Bell Telephone Labor Inc | Automatic equalizer for digital transmission systems |
| GB1239061A (es) * | 1968-10-30 | 1971-07-14 | ||
| US3578914A (en) * | 1969-04-09 | 1971-05-18 | Lynch Communication Systems | Equalizer with automatic line build-out |
| JPS527304B1 (es) * | 1969-08-29 | 1977-03-01 | ||
| FR2238300B1 (es) * | 1973-07-20 | 1976-11-12 | Lignes Telegraph Telephon | |
| DE3241185A1 (de) * | 1982-11-08 | 1984-05-10 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Schaltungsanordnung zur daempfungseinstellung in fernmelde-, insbesondere fernsprechverbindungswesen |
| US4488126A (en) * | 1982-11-18 | 1984-12-11 | Northern Telecom Limited | Equalizer arrangement for mixed-gauge cables |
| US4555788A (en) * | 1984-02-23 | 1985-11-26 | Itt Corporation | Multiple rate baseband receiver |
| JPS6162241A (ja) * | 1984-09-04 | 1986-03-31 | Nec Corp | スイツチトキヤパシタ自動線路等化器 |
| FR2570235B1 (fr) * | 1984-09-07 | 1989-07-28 | Trt Telecom Radio Electr | Circuit d'interface analogique monolithique entre un processeur de signal et un reseau de telecommunication |
| US4827505A (en) * | 1985-08-20 | 1989-05-02 | Fujitsu Limited | Subscriber line interface circuit |
| US4745624A (en) * | 1985-11-29 | 1988-05-17 | Conklin Instrument Corporation | Automatic line buildout |
| US4785265A (en) * | 1987-10-01 | 1988-11-15 | The Babcock & Wilcox Company | Enhanced automatic line build out |
-
1988
- 1988-11-02 US US07/266,082 patent/US4964116A/en not_active Expired - Fee Related
-
1989
- 1989-09-27 CA CA000613765A patent/CA1337078C/en not_active Expired - Fee Related
- 1989-10-31 DE DE68925514T patent/DE68925514T2/de not_active Expired - Fee Related
- 1989-10-31 AT AT89120157T patent/ATE133525T1/de not_active IP Right Cessation
- 1989-10-31 ES ES89120157T patent/ES2082765T3/es not_active Expired - Lifetime
- 1989-10-31 EP EP89120157A patent/EP0367208B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4964116A (en) | 1990-10-16 |
| EP0367208A3 (en) | 1991-11-13 |
| EP0367208B1 (en) | 1996-01-24 |
| DE68925514T2 (de) | 1996-06-05 |
| DE68925514D1 (de) | 1996-03-07 |
| ATE133525T1 (de) | 1996-02-15 |
| EP0367208A2 (en) | 1990-05-09 |
| CA1337078C (en) | 1995-09-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG2A | Definitive protection |
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