ES2087968T3 - Interconexion de circuito integrado. - Google Patents

Interconexion de circuito integrado.

Info

Publication number
ES2087968T3
ES2087968T3 ES91302094T ES91302094T ES2087968T3 ES 2087968 T3 ES2087968 T3 ES 2087968T3 ES 91302094 T ES91302094 T ES 91302094T ES 91302094 T ES91302094 T ES 91302094T ES 2087968 T3 ES2087968 T3 ES 2087968T3
Authority
ES
Spain
Prior art keywords
integrated circuit
circuit interconnection
tracer
closure
track
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91302094T
Other languages
English (en)
Inventor
Ajit Singh Manocha
Virendra Vir Singh Rana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2087968T3 publication Critical patent/ES2087968T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

SE PRESENTA UN CIRCUITO INTEGRADO Y EL METODO DE FABRICACION DEL MISMO. LA INVENCION PROPORCIONA UNA CAPA LIMITE DE GRABACION ENTRE UN CIERRE FORMADO EN UNA VIA Y EL TRAZADOR DE RECUBRIMIENTO. LA CAPA ANTERIORMENTE MENCIONADA CUMPLE UNA VARIEDAD DE FUNCIONES, INCLUYENDO LA PROTECCION DEL CIERRE DURANTE EL PROCESO DE ACTUACION DE ACIDO QUE DEFINE EL TRAZADOR.
ES91302094T 1990-03-23 1991-03-13 Interconexion de circuito integrado. Expired - Lifetime ES2087968T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49829290A 1990-03-23 1990-03-23

Publications (1)

Publication Number Publication Date
ES2087968T3 true ES2087968T3 (es) 1996-08-01

Family

ID=23980426

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91302094T Expired - Lifetime ES2087968T3 (es) 1990-03-23 1991-03-13 Interconexion de circuito integrado.

Country Status (5)

Country Link
EP (1) EP0448276B1 (es)
JP (1) JPH04223358A (es)
DE (1) DE69119953T2 (es)
ES (1) ES2087968T3 (es)
HK (1) HK180196A (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0566253A1 (en) * 1992-03-31 1993-10-20 STMicroelectronics, Inc. Method for forming contact structures in integrated circuits
FR2691836B1 (fr) * 1992-05-27 1997-04-30 Ela Medical Sa Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant.
US5652180A (en) * 1993-06-28 1997-07-29 Kawasaki Steel Corporation Method of manufacturing semiconductor device with contact structure
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
DE69527344T2 (de) * 1994-12-29 2003-02-27 Stmicroelectronics, Inc. Verfahren zur Herstellung einer Halbleiterverbindungsstruktur
US6001729A (en) * 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
JPH08191054A (ja) * 1995-01-10 1996-07-23 Kawasaki Steel Corp 半導体装置及びその製造方法
KR100272673B1 (ko) * 1998-06-02 2000-11-15 윤종용 반도체 메모리 장치의 제조 방법
US6372633B1 (en) * 1998-07-08 2002-04-16 Applied Materials, Inc. Method and apparatus for forming metal interconnects
US6974766B1 (en) * 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6245655B1 (en) * 1999-04-01 2001-06-12 Cvc Products, Inc. Method for planarized deposition of a material

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3881032T2 (de) * 1988-05-26 1993-11-25 Fairchild Semiconductor Verbindungssystem von hoher Leistungsfähigkeit für eine integrierte Schaltung.

Also Published As

Publication number Publication date
EP0448276A2 (en) 1991-09-25
EP0448276B1 (en) 1996-06-05
JPH04223358A (ja) 1992-08-13
EP0448276A3 (en) 1992-07-08
HK180196A (en) 1996-10-04
DE69119953D1 (de) 1996-07-11
DE69119953T2 (de) 1997-01-23

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