ES2091960T3 - Sintetizador de circuito con enganche de fase para uso en un sistema de comunicacion de multiplexado con division de tiempo. - Google Patents

Sintetizador de circuito con enganche de fase para uso en un sistema de comunicacion de multiplexado con division de tiempo.

Info

Publication number
ES2091960T3
ES2091960T3 ES92102402T ES92102402T ES2091960T3 ES 2091960 T3 ES2091960 T3 ES 2091960T3 ES 92102402 T ES92102402 T ES 92102402T ES 92102402 T ES92102402 T ES 92102402T ES 2091960 T3 ES2091960 T3 ES 2091960T3
Authority
ES
Spain
Prior art keywords
pll
time division
communication system
multiplexed communication
synthesizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92102402T
Other languages
English (en)
Inventor
Ryuhei Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of ES2091960T3 publication Critical patent/ES2091960T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

SE PROPORCIONA UN INTERRUPTOR ANALOGICO EN UN SINTETIZADOR DE CIRCUITO EN FASE CERRADA (PLL) UTILIZANDO CIRCUITOS DIGITALES DIRECTOS DE SINTETIZADOR (DDS), PARA ABRIR UN PLL. EL PLL SE CIERRA PARA HACER OPERATIVO EL CIRCUITO DDS Y UN DIVISOR DE FRECUENCIA FIJA SITUADO ENTRE UNA RANURA DE TIEMPO EN REPOSO DE CADA ESTRUCTURA MULTIPLEXORA DE DIVISION DEL TIEMPO (TDM). PARA EL RESTO DE LA ESTRUCTURA, EL OSCILADOR DE TENSION CONTROLADA SITUADO EN EL PLL SE MANTIENE EN UN "ESTADO SOSTENIDO".
ES92102402T 1991-02-14 1992-02-13 Sintetizador de circuito con enganche de fase para uso en un sistema de comunicacion de multiplexado con division de tiempo. Expired - Lifetime ES2091960T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3042738A JP2806059B2 (ja) 1991-02-14 1991-02-14 位相同期ループシンセサイザ

Publications (1)

Publication Number Publication Date
ES2091960T3 true ES2091960T3 (es) 1996-11-16

Family

ID=12644370

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92102402T Expired - Lifetime ES2091960T3 (es) 1991-02-14 1992-02-13 Sintetizador de circuito con enganche de fase para uso en un sistema de comunicacion de multiplexado con division de tiempo.

Country Status (7)

Country Link
US (1) US5175511A (es)
EP (1) EP0499245B1 (es)
JP (1) JP2806059B2 (es)
AU (1) AU640596B2 (es)
CA (1) CA2061194C (es)
DE (1) DE69213499T2 (es)
ES (1) ES2091960T3 (es)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994020888A2 (en) * 1993-03-10 1994-09-15 National Semiconductor Corporation Radio frequency telecommunications transceiver
EP0691746A1 (en) * 1993-03-18 1996-01-10 Kabushiki Kaisha Toshiba Frequency synthesizer
JPH0817326B2 (ja) * 1993-03-30 1996-02-21 日本電気株式会社 周波数シンセサイザ
US5598405A (en) * 1994-01-25 1997-01-28 Alps Electric Co., Ltd. Time division multiple access time division duplex type transmitter-receiver
US5598440A (en) * 1994-11-08 1997-01-28 Mpb Technologies Inc. DDS driven DDS synthesizer for generating sinewave waveforms with reduced spurious signal levels
GB2295930B (en) * 1994-12-06 1999-11-24 Motorola Ltd Method and apparatus for implementing frequency hopping in a TDMA system
DE19700249A1 (de) * 1997-01-07 1998-07-09 Helmut Meier Vorrichtung für die Erzeugung und/oder den Empfang eines modulierten Funksignals
JP3088323B2 (ja) * 1997-02-18 2000-09-18 埼玉日本電気株式会社 Ｔｄｍａ方式無線機とシンセサイザ出力レベル調整回路
DE19727810C1 (de) * 1997-06-30 1999-02-18 Siemens Ag Hochfrequenz-Signalgenerator
JPH11225090A (ja) * 1998-02-06 1999-08-17 Alps Electric Co Ltd 時分割双方向通信装置
GB2335807B (en) * 1998-03-24 2001-12-12 Ericsson Telefon Ab L M Demodulator circuits
US6628656B1 (en) * 1999-08-09 2003-09-30 Cypress Semiconductor Corp. Circuit, method and/or architecture for improving the performance of a serial communication link
US6456135B1 (en) * 2000-09-19 2002-09-24 Thomson Licensing S.A. System and method for single pin reset a mixed signal integrated circuit
DE10102725C2 (de) * 2001-01-22 2003-04-24 Infineon Technologies Ag Verfahren zum Betreiben einer PLL-Frequenzsyntheseschaltung
US7302237B2 (en) * 2002-07-23 2007-11-27 Mercury Computer Systems, Inc. Wideband signal generators, measurement devices, methods of signal generation, and methods of signal analysis
JP5034306B2 (ja) * 2006-04-28 2012-09-26 富士通株式会社 周波数変調回路及びｆｍ−ｃｗレーダ装置並びに通信統合レーダ装置
JP4668868B2 (ja) * 2006-08-21 2011-04-13 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
US20080212658A1 (en) * 2007-03-01 2008-09-04 Ahmadreza Rofougaran Method and system for communication of signals using a direct digital frequency synthesizer (ddfs)
KR102047922B1 (ko) 2013-02-07 2019-11-25 삼성디스플레이 주식회사 플렉서블 기판, 플렉서블 기판의 제조 방법, 플렉서블 표시 장치, 및 플렉서블 표시 장치 제조 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4061979A (en) 1975-10-20 1977-12-06 Digital Communications Corporation Phase locked loop with pre-set and squelch
US4331941A (en) * 1980-02-29 1982-05-25 Hewlett-Packard Company Digital phase domain amplitude modulation method and apparatus
CA1325251C (en) * 1988-09-02 1993-12-14 Shigeki Saito Frequency synthesizer
US4965533A (en) 1989-08-31 1990-10-23 Qualcomm, Inc. Direct digital synthesizer driven phase lock loop frequency synthesizer

Also Published As

Publication number Publication date
CA2061194A1 (en) 1992-08-15
EP0499245A2 (en) 1992-08-19
DE69213499T2 (de) 1997-02-06
DE69213499D1 (de) 1996-10-17
EP0499245B1 (en) 1996-09-11
US5175511A (en) 1992-12-29
EP0499245A3 (en) 1993-01-20
CA2061194C (en) 1996-01-30
AU640596B2 (en) 1993-08-26
JPH04260219A (ja) 1992-09-16
JP2806059B2 (ja) 1998-09-30
AU1098792A (en) 1992-08-20

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