ES2104675T3 - Contacto de circuito integrado. - Google Patents

Contacto de circuito integrado.

Info

Publication number
ES2104675T3
ES2104675T3 ES91310679T ES91310679T ES2104675T3 ES 2104675 T3 ES2104675 T3 ES 2104675T3 ES 91310679 T ES91310679 T ES 91310679T ES 91310679 T ES91310679 T ES 91310679T ES 2104675 T3 ES2104675 T3 ES 2104675T3
Authority
ES
Spain
Prior art keywords
silicone
integrated circuit
aluminum
circuit contact
additional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91310679T
Other languages
English (en)
Inventor
Sailesh Chittipeddi
William Thomas Cochran
Michael James Kelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2104675T3 publication Critical patent/ES2104675T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

SE HA DESCUBIERTO UN METODO DE FABRICACION DE UN CIRCUITO INTEGRADO, QUE INCLUYE LA FORMACION DE UNA CAPA ADICIONAL (E. G., 23, 25) DE SILICONA EN LAS APERTURAS EN CONTACTO, QUE SON RELLENADAS CON ALUMINIO (E. G., 21). LA CAPA ADICIONAL DE SILICONA (E. G., 23, 25), ES PUESTA ADYACENTE A LA CAPA DE ALUMINIO, PARA PROVEER SILICONA PARA SU INTERDIFUSION DENTRO DEL ALUMINIO, Y ASI PODER EVITAR LA PERFORACION EN LA UNION. LA SILICONA ADICCIONAL PUEDE SER IMPLANTADA POR IONES, O POR CAPAS FORMADAS SEPARADAMENTE (E. G., 23, 25).
ES91310679T 1990-11-29 1991-11-20 Contacto de circuito integrado. Expired - Lifetime ES2104675T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62114290A 1990-11-29 1990-11-29

Publications (1)

Publication Number Publication Date
ES2104675T3 true ES2104675T3 (es) 1997-10-16

Family

ID=24488903

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91310679T Expired - Lifetime ES2104675T3 (es) 1990-11-29 1991-11-20 Contacto de circuito integrado.

Country Status (3)

Country Link
EP (1) EP0488576B1 (es)
DE (1) DE69127347T2 (es)
ES (1) ES2104675T3 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0126457B1 (ko) * 1992-01-08 1997-12-26 기타오카 다카시 집적회로, 그 제조방법 및 그 박막형성장치
EP0572212A3 (en) * 1992-05-29 1994-05-11 Sgs Thomson Microelectronics Method to form silicon doped cvd aluminium
KR970052186A (ko) * 1995-12-04 1997-07-29 김주용 반도체 소자 제조 방법
US6025264A (en) * 1998-02-09 2000-02-15 United Microelectronics Corp. Fabricating method of a barrier layer
KR100376810B1 (ko) * 1998-09-23 2003-06-12 유나이티드 마이크로일렉트로닉스 코퍼레이션 배리어막을갖는반도체소자및그제조방법
WO2009138906A2 (en) 2008-05-12 2009-11-19 Nxp B.V. Mems devices and fabrication thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450041A (en) * 1982-06-21 1984-05-22 The United States Of America As Represented By The Secretary Of The Navy Chemical etching of transformed structures
DE3930655A1 (de) * 1988-09-13 1990-03-22 Mitsubishi Electric Corp Halbleitervorrichtung mit vielschichtig gestapelter verbindungsschicht und verfahren zu deren herstellung

Also Published As

Publication number Publication date
EP0488576B1 (en) 1997-08-20
DE69127347T2 (de) 1998-02-05
EP0488576A1 (en) 1992-06-03
DE69127347D1 (de) 1997-09-25

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