ES2110397T3 - Circuito integrado con enlace de cubetas. - Google Patents

Circuito integrado con enlace de cubetas.

Info

Publication number
ES2110397T3
ES2110397T3 ES88305407T ES88305407T ES2110397T3 ES 2110397 T3 ES2110397 T3 ES 2110397T3 ES 88305407 T ES88305407 T ES 88305407T ES 88305407 T ES88305407 T ES 88305407T ES 2110397 T3 ES2110397 T3 ES 2110397T3
Authority
ES
Spain
Prior art keywords
source
silicide
cubet
connect
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88305407T
Other languages
English (en)
Inventor
Min-Liang Chen
Chung Wai Leung
Daniel Mark Wroge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
AT&T Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Inc filed Critical AT&T Inc
Application granted granted Critical
Publication of ES2110397T3 publication Critical patent/ES2110397T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H10P14/414—Deposition of metallic or metal-silicide materials of metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

CUANDO SE FABRICAN CIRCUITOS LOGICOS CMOS, POR EJEMPLO UN INVERSOR, ES CON FRECUENCIA NECESARIO CONECTAR LAS FUENTES DE LOS TRANSISTORES DE LOS CANALES P Y N A SUS CUBETAS RESPECTIVAS (N Y P, RESPECTIVAMENTE). LA TECNICA ANTERIOR EXIGIA BIEN UNA GRAN VENTANA DE CONTACTO CUBRIENDO TANTO LA FUENTE COMO LAS CUBETAS O BIEN DOS VENTANAS DE CONTACTO DE TAMAÑO ESTANDAR. LA TECNICA DESCRITA AQUI FORMA LA CONEXION UTILIZANDO LA MISMA CAPA DE SILICIURO (106,107,112,116) QUE SE FORMA EN LAS REGIONES FUENTE/DESCARGA, LA CUAL TAMBIEN FORMA UN SILICIURO DE PUERTA (108,117) EN EL PROCESO DE SILICIURO AUTOALINEADO. ASI, PUEDE EMPLEARSE UNA VENTANA CONVENCIONAL PARA CONECTAR LA UNION DE SILICIURO DE LA CUBETA (Y, POR LO TANTO, LAS REGIONES FUENTE/CUBETA) A UN CONDUCTO DE SUMINISTRO DE CORRIENTE (114,128). DE ESTA FORMA SE CONSIGUE AHORRAR ESPACIO Y MAYOR LIBERTAD PARA COLOCAR LA FUENTE ENERGETICA.
ES88305407T 1987-06-22 1988-06-14 Circuito integrado con enlace de cubetas. Expired - Lifetime ES2110397T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6523587A 1987-06-22 1987-06-22

Publications (1)

Publication Number Publication Date
ES2110397T3 true ES2110397T3 (es) 1998-02-16

Family

ID=22061276

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88305407T Expired - Lifetime ES2110397T3 (es) 1987-06-22 1988-06-14 Circuito integrado con enlace de cubetas.

Country Status (5)

Country Link
EP (1) EP0296747B1 (es)
JP (1) JPS6421950A (es)
KR (1) KR920003800B1 (es)
DE (1) DE3856086T2 (es)
ES (1) ES2110397T3 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG108807A1 (en) 1989-02-14 2005-02-28 Seiko Epson Corp A semiconductor device and its manufacturing method
KR100214113B1 (ko) * 1993-05-11 1999-08-02 오가사와라 쇼헤이 터널라이너 그 제조방법 및 그 제조장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208773A (ja) * 1983-05-12 1984-11-27 Nec Corp 半導体装置の製造方法
JPS60120571A (ja) * 1983-12-05 1985-06-28 Hitachi Ltd 半導体集積回路装置
US4677739A (en) * 1984-11-29 1987-07-07 Texas Instruments Incorporated High density CMOS integrated circuit manufacturing process

Also Published As

Publication number Publication date
KR920003800B1 (ko) 1992-05-14
DE3856086D1 (de) 1998-01-29
EP0296747B1 (en) 1997-12-17
DE3856086T2 (de) 1998-04-09
EP0296747A1 (en) 1988-12-28
KR890001201A (ko) 1989-03-18
JPS6421950A (en) 1989-01-25

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