ES2111776T3 - Disposicion para la transmision de datos con un sistema de bus paralelo. - Google Patents

Disposicion para la transmision de datos con un sistema de bus paralelo.

Info

Publication number
ES2111776T3
ES2111776T3 ES93923453T ES93923453T ES2111776T3 ES 2111776 T3 ES2111776 T3 ES 2111776T3 ES 93923453 T ES93923453 T ES 93923453T ES 93923453 T ES93923453 T ES 93923453T ES 2111776 T3 ES2111776 T3 ES 2111776T3
Authority
ES
Spain
Prior art keywords
units
bus system
access
data
response signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93923453T
Other languages
English (en)
Inventor
Michael Abert
Siegfried Block
Johannes Bozenhardt
Franz Leigsnering
Werner Pfatteicher
Franz-Clemens Schewe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2111776T3 publication Critical patent/ES2111776T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)

Abstract

LA INVENCION SE REFIERE A UNA DISPOSICION PARA TRANSMISION DE DATOS CON UN SISTEMA BUS EN PARALELO, CONSISTIENDO EN DIRECCIONES, DATOS Y BUSES DE CONTROL, Y CON VARIAS UNIDADES (3,4,5,6) CONECTADAS CON EL. UNA PRIMERA LINEA (1) DE CONTROL SE UTILIZA PARA ENVIAR UNA SEÑAL DE RECONOCIMIENTO (READY), CON LA QUE UNA O MAS UNIDADES SON DIRIGIDAS POR MEDIO DE UNA PRIMERA UNIDAD CON UN ACCESO DE RECONOCIMIENTO DE CICLOS DE ACCESO. UNA SEGUNDA LINEA (2) DE CONTROL SE UTILIZA PARA DETECTAR LOS ERRORES DE DIRECCIONAMIENTO Y LOS ACCESOS A LAS UNIDADES NO EXISTENTES Y PARA REALIZAR EN LA PRIMERA UNIDAD UNA SEÑAL (SR) DE RESPUESTA A PARTIR DE LAS OTRAS INDICANDO SI UNA DE LAS UNIDADES ACEPTADAS HA SIDO DIRECCIONADA. PARA REALZAR ESTO LA SEÑAL (SR) DE RESPUESTA DISPONE DE UNA SITUACION DOMINANTE Y RECESIVA. DURANTE UN CICLO DE ACCESO SOLO UNIDADES DIRECCIONADAS GENERAN UN ESTADO DOMINANTE. LA SEÑAL (SR) DE RESPUESTA SE UTILIZA TAMBIEN PARA ACCESO DE PUNTOS MULTIPLES SINCRONOS. LA INVENCION SE UTILIZA ENSISTEMA BUS.
ES93923453T 1992-11-04 1993-10-29 Disposicion para la transmision de datos con un sistema de bus paralelo. Expired - Lifetime ES2111776T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4237259A DE4237259A1 (de) 1992-11-04 1992-11-04 Anordnung zur Datenübertragung mit einem parallelen Bussystem

Publications (1)

Publication Number Publication Date
ES2111776T3 true ES2111776T3 (es) 1998-03-16

Family

ID=6472097

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93923453T Expired - Lifetime ES2111776T3 (es) 1992-11-04 1993-10-29 Disposicion para la transmision de datos con un sistema de bus paralelo.

Country Status (7)

Country Link
US (1) US5617309A (es)
EP (1) EP0667014B1 (es)
JP (1) JP2660980B2 (es)
AT (1) ATE161981T1 (es)
DE (3) DE4237259A1 (es)
ES (1) ES2111776T3 (es)
WO (1) WO1994010631A1 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101153712B1 (ko) * 2005-09-27 2012-07-03 삼성전자주식회사 멀티-포트 ｓｄｒａｍ 엑세스 제어장치와 제어방법
FR3100628B1 (fr) * 2019-09-10 2023-04-14 St Microelectronics Grenoble 2 Communication par bus CAN

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128883A (en) * 1977-09-30 1978-12-05 Ncr Corporation Shared busy means in a common bus environment
US4310896A (en) * 1979-11-13 1982-01-12 General Electric Company Method of interfacing remote units to a central microprocessor
US4710871A (en) * 1982-11-01 1987-12-01 Ncr Corporation Data transmitting and receiving apparatus
US4635186A (en) * 1983-06-20 1987-01-06 International Business Machines Corporation Detection and correction of multi-chip synchronization errors
DE3333807A1 (de) * 1983-09-19 1985-04-11 Siemens AG, 1000 Berlin und 8000 München Speicherprogrammierbares automatisierungsgeraet
JPH0276057A (ja) * 1988-09-13 1990-03-15 Toshiba Corp Ｉ／ｏリカバリ方式
US5070443A (en) * 1989-09-11 1991-12-03 Sun Microsystems, Inc. Apparatus for write handshake in high-speed asynchronous bus interface

Also Published As

Publication number Publication date
DE4237259A1 (de) 1994-05-05
JPH07508610A (ja) 1995-09-21
EP0667014B1 (de) 1998-01-07
EP0667014A1 (de) 1995-08-16
DE9321462U1 (de) 1998-04-23
JP2660980B2 (ja) 1997-10-08
WO1994010631A1 (de) 1994-05-11
ATE161981T1 (de) 1998-01-15
DE59307959D1 (de) 1998-02-12
US5617309A (en) 1997-04-01

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