ES2112266T3 - Aparato para controlar el acceso a un bus de datos - Google Patents

Aparato para controlar el acceso a un bus de datos

Info

Publication number
ES2112266T3
ES2112266T3 ES91306702T ES91306702T ES2112266T3 ES 2112266 T3 ES2112266 T3 ES 2112266T3 ES 91306702 T ES91306702 T ES 91306702T ES 91306702 T ES91306702 T ES 91306702T ES 2112266 T3 ES2112266 T3 ES 2112266T3
Authority
ES
Spain
Prior art keywords
data bus
processing unit
host
local
computing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91306702T
Other languages
English (en)
Inventor
Douglas D Gephardt
James R Macdonald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2112266T3 publication Critical patent/ES2112266T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Selective Calling Equipment (AREA)
  • Multi Processors (AREA)

Abstract

UN APARATO PARA UTILIZAR CON UN SISTEMA DE ORDENADOR PRINCIPAL PARA CONTROLAR EL ACCESO HACIA UN PRIMER BUS DE DATOS QUE SE ENCUENTRA EN EL EXTERIOR DEL SISTEMA DE ORDENADOR PRINCIPAL Y CUYO PRIMER BUS DE DATOS ESTA OPERATIVAMENTE CONECTADO CON UN SEGUNDO BUS DE DATOS INTERNO AL SISTEMA DE ORDENADOR PRINCIPAL. EL APARATO COMPRENDE UNA UNIDAD DE PROCESAMIENTO LOCAL CONFIGURADA SUSTANCIALMENTE IGUAL QUE LA UNIDAD DE PROCESAMIENTO PRINCIPAL Y ESTA GUIADA POR UN PROGRAMA LOCAL INDEPENDIENTE DISTINTO DEL PROGRAMA DE PROCESAMIENTO PRINCIPAL QUE GUIA A LA UNIDAD DE PROCESAMIENTO PRINCIPAL. EL APARATO COMPRENDE TAMBIEN, UN CIRCUITO DE PROCESAMIENTO SUPLEMENTARIO PARA PROCESAR LA INFORMACION, DICHO CIRCUITO SUPLEMENTARIO RESPONDE A LA UNIDAD DE PROCESAMIENTO PRINCIPAL Y A LA UNIDAD DE PROCESAMIENTO LOCAL PARA DETERMINAR SI LA UNIDAD DE PROCESAMIENTO PRINCIPAL O LA DE PROCESAMIENTO LOCAL TIENEN O NO ACCESO OPERATIVO AL PRIMER BUS DE DATOS. EN SU INCORPORACION PREFERENTE, EL PRIMERO Y SEGUNDO BUS DE DATOS ESTAN CONECTADOS OPERATIVAMENTE MEDIANTE UN CIRCUITO AMORTIGUADOR CONFIGURABLE PARA EFECTUAR LA CONEXION DE LOS BUSES DE DATOS. ADEMAS EN LA INCORPORACION PREFERENTE DE LA INVENCION, EL CIRCUITO DE PROCESAMIENTO SUPLEMENTARIO GENERA UNA SEÑAL DE INTERVENCION EN RESPUESTA A LA UNIDAD DE PROCESAMIENTO LOCAL, EL CIRCUITO AMORTIGUADOR RESPONDE A LA SEÑAL DE INTERVENCION AL CONFIGURARSE ADECUADAMENTE PARA PROPORCIONAR AL APARATO UN ACCESO OPERATIVO AL SEGUNDO BUS DE DATOS.
ES91306702T 1990-08-31 1991-07-23 Aparato para controlar el acceso a un bus de datos Expired - Lifetime ES2112266T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/576,061 US5218681A (en) 1990-08-31 1990-08-31 Apparatus for controlling access to a data bus

Publications (1)

Publication Number Publication Date
ES2112266T3 true ES2112266T3 (es) 1998-04-01

Family

ID=24302809

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91306702T Expired - Lifetime ES2112266T3 (es) 1990-08-31 1991-07-23 Aparato para controlar el acceso a un bus de datos

Country Status (6)

Country Link
US (1) US5218681A (es)
EP (1) EP0473277B1 (es)
JP (1) JP3379762B2 (es)
AT (1) ATE163484T1 (es)
DE (1) DE69128948T2 (es)
ES (1) ES2112266T3 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9019001D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station including a direct memory access controller and interfacing means to microchannel means
GB9018992D0 (en) * 1990-08-31 1990-10-17 Ncr Co Internal bus for work station interfacing means
US5333277A (en) * 1992-01-10 1994-07-26 Exportech Trading Company Data buss interface and expansion system
US5816921A (en) * 1994-09-27 1998-10-06 Sega Enterprises, Ltd. Data transferring device and video game apparatus using the same
US5634112A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation Memory controller having precharge prediction based on processor and PCI bus cycles
US5909560A (en) * 1995-06-06 1999-06-01 National Semiconductor Corporation Target peripheral device detection in a multi-bus system
US5673400A (en) * 1995-06-06 1997-09-30 National Semiconductor Corporation Method and apparatus for identifying and controlling a target peripheral device in a multiple bus system
US7076584B2 (en) * 2003-05-09 2006-07-11 Freescale Semiconductor, Inc. Method and apparatus for interconnecting portions of circuitry within a data processing system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646232A (en) * 1984-01-03 1987-02-24 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system
US4777591A (en) * 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
EP0297931B1 (en) * 1987-06-29 1995-12-13 Digital Equipment Corporation Bus adapter unit for digital data processing system
EP0335502A3 (en) * 1988-03-30 1991-07-03 Advanced Micro Devices, Inc. Microcontroller and associated method
US5129090A (en) * 1988-05-26 1992-07-07 Ibm Corporation System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration
US4935868A (en) * 1988-11-28 1990-06-19 Ncr Corporation Multiple port bus interface controller with slave bus
US5083259A (en) * 1988-12-07 1992-01-21 Xycom, Inc. Computer bus interconnection device
US5088028A (en) * 1989-04-07 1992-02-11 Tektronix, Inc. Lock converting bus-to-bus interface system

Also Published As

Publication number Publication date
US5218681A (en) 1993-06-08
DE69128948T2 (de) 1998-09-17
EP0473277A3 (es) 1994-01-19
EP0473277B1 (en) 1998-02-25
ATE163484T1 (de) 1998-03-15
DE69128948D1 (de) 1998-04-02
EP0473277A2 (en) 1992-03-04
JPH04332063A (ja) 1992-11-19
JP3379762B2 (ja) 2003-02-24

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