JPS6476343A - Cache memory control system - Google Patents

Cache memory control system

Info

Publication number
JPS6476343A
JPS6476343A JP62235522A JP23552287A JPS6476343A JP S6476343 A JPS6476343 A JP S6476343A JP 62235522 A JP62235522 A JP 62235522A JP 23552287 A JP23552287 A JP 23552287A JP S6476343 A JPS6476343 A JP S6476343A
Authority
JP
Japan
Prior art keywords
invalidation
data
area
control
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235522A
Other languages
Japanese (ja)
Inventor
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62235522A priority Critical patent/JPS6476343A/en
Publication of JPS6476343A publication Critical patent/JPS6476343A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To decrease invalidation control and to improve the processing speed in a cache memory control system by setting a cache invalidation area where a processor has no handling at a main memory and reading/writing transferred data. CONSTITUTION:Address data set at a setting register 21 is compared with the address data outputted from a processor 4. An address checking part 22 shows the invalidation of cache control to a main memory 2 when access given to a cache invalidation area 2a from the processor 4 is detected. An invalidation control part 20 stops the invalidation control when circuit control parts 7 and 8 perform the writing job in the area 2a. The data part of the data which is transferred between a host device and a terminal equipment is received by the area 2a. At the same time, data invalidation processing to the memory 2 is stopped when a writing action carried out by direct memory access given to the area 2a is detected. Thus it is possible to improve the deterioration in data invalidation processing speed of the memory 2.
JP62235522A 1987-09-18 1987-09-18 Cache memory control system Pending JPS6476343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235522A JPS6476343A (en) 1987-09-18 1987-09-18 Cache memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235522A JPS6476343A (en) 1987-09-18 1987-09-18 Cache memory control system

Publications (1)

Publication Number Publication Date
JPS6476343A true JPS6476343A (en) 1989-03-22

Family

ID=16987222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235522A Pending JPS6476343A (en) 1987-09-18 1987-09-18 Cache memory control system

Country Status (1)

Country Link
JP (1) JPS6476343A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04330540A (en) * 1991-05-02 1992-11-18 Mitsubishi Electric Corp Microcomputer control system
JPWO2012117701A1 (en) * 2011-03-02 2014-07-07 日本電気株式会社 Data control system, data control method, and data control program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04330540A (en) * 1991-05-02 1992-11-18 Mitsubishi Electric Corp Microcomputer control system
JPWO2012117701A1 (en) * 2011-03-02 2014-07-07 日本電気株式会社 Data control system, data control method, and data control program

Similar Documents

Publication Publication Date Title
JPS56140452A (en) Memory protection system
SE9101325D0 (en) PROCEDURE TO INCREASE DATA PROCESSING RATE IN COMPUTER SYSTEM
KR830009520A (en) Terminal connection system
JPS57113162A (en) High-speed external storage device
EP0833341A3 (en) Circuit for controlling writing data to memory
KR900000480B1 (en) Buffer memory control method into data processing apparatus
GB8806742D0 (en) Data processing apparatus with memory control function based on cpu state detection
JPS648580A (en) Memory device for electronic equipment
JPS6476343A (en) Cache memory control system
JPS55123739A (en) Memory content prefetch control system
JPS5731049A (en) Information processing equipment
JPS559228A (en) Memory request control system
JPS51118335A (en) Partly writing system
JPS57200985A (en) Buffer memory device
JPS6436339A (en) Self-diagnosis system
JPS5663652A (en) Information processing unit
JPS647144A (en) Cache memory control system
JPS5734264A (en) Multiprocessor
JPS6455266A (en) External character font register data recorder
JPS57203157A (en) Data processor
JPS5757369A (en) Access control system
JPS6415844A (en) Memory device
JPS648470A (en) Input/output controller
JPS55103662A (en) Data processing unit
JPS5613575A (en) Memory system