ES2136116T3 - Sistema de transmision de datos entre un bus de ordenador y una red en forma de anillo de alta capacidad. - Google Patents

Sistema de transmision de datos entre un bus de ordenador y una red en forma de anillo de alta capacidad.

Info

Publication number
ES2136116T3
ES2136116T3 ES93402222T ES93402222T ES2136116T3 ES 2136116 T3 ES2136116 T3 ES 2136116T3 ES 93402222 T ES93402222 T ES 93402222T ES 93402222 T ES93402222 T ES 93402222T ES 2136116 T3 ES2136116 T3 ES 2136116T3
Authority
ES
Spain
Prior art keywords
data transmission
transmission system
network
computer bus
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93402222T
Other languages
English (en)
Inventor
Paul Ravaux
Pascal Urien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Application granted granted Critical
Publication of ES2136116T3 publication Critical patent/ES2136116T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

SISTEMA DE TRANSMISION DE DATOS ENTRE UN BUS (PSB) DE ORDENADOR Y UNA RED (RE) QUE COMPRENDE: UN DISPOSITIVO DE ACOPLAMIENTO (GPU) UNIDO AL BUS Y QUE COMUNICA POR UN INTERFACE CON UN DISPOSITIVO ADAPTADOR (DEA) CONECTADO A LA RED, UN PRIMER MICROPROCESADOR (CPU1); UNOS MEDIOS DE TRANSFERENCIA DE TRAMAS DESDE EL BUS HACIA EL DISPOSITIVO ADAPTADOR QUE INCLUYE UNA MEMORIA DE DOBLE PASO. EL DISPOSITIVO ADAPTADOR COMPORTA UN SEGUNDO MICROPROCESADOR (CPU2) CARACTERIZADO EN QUE EL INTERFACE ESTA CONSTITUIDO POR FILAS DE MANDOS (F1 A F4) DISPUESTAS EN LA DICHA MEMORIA, EL SEGUNDO PROCESADOR DE GESTION TRATA UNOS MODULOS LOGICOS (ML1, .... ML10) INDEPENDIENTES ENTRE ELLOS, PARA ADMINISTRAR LA EMISION Y LA RECEPCION DE TRAMAS ESPECIFICAS DE LA RED, Y COMUNICANDO POR MEDIO DE BUZONES (BAL1, ETC...) INCLUIDOS EN EL SEGUNDO PROCESADOR Y/O EN LAS FILAS DE MANDOS. APLICABLE A LOS PROCESADORES DE COMUNICACION.
ES93402222T 1992-09-16 1993-09-13 Sistema de transmision de datos entre un bus de ordenador y una red en forma de anillo de alta capacidad. Expired - Lifetime ES2136116T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9211054A FR2695740B1 (fr) 1992-09-16 1992-09-16 Système de transmission de données entre un bus d'ordinateur et un réseau en forme d'anneau à très haut débit.

Publications (1)

Publication Number Publication Date
ES2136116T3 true ES2136116T3 (es) 1999-11-16

Family

ID=9433577

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93402222T Expired - Lifetime ES2136116T3 (es) 1992-09-16 1993-09-13 Sistema de transmision de datos entre un bus de ordenador y una red en forma de anillo de alta capacidad.

Country Status (6)

Country Link
US (1) US5561812A (es)
EP (1) EP0588703B1 (es)
JP (1) JPH07120320B2 (es)
DE (1) DE69325135T2 (es)
ES (1) ES2136116T3 (es)
FR (1) FR2695740B1 (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5799190A (en) * 1994-08-09 1998-08-25 Apple Computer, Inc. Communications coprocessor for realizing bidirectional isochronous communications link with host computer
JPH0887459A (ja) * 1994-09-19 1996-04-02 Fujitsu Ltd バックグラウンド通信方式
US5996024A (en) * 1998-01-14 1999-11-30 Emc Corporation Method and apparatus for a SCSI applications server which extracts SCSI commands and data from message and encapsulates SCSI responses to provide transparent operation
US7093127B2 (en) * 2001-08-09 2006-08-15 Falconstor, Inc. System and method for computer storage security
US6715098B2 (en) 2001-02-23 2004-03-30 Falconstor, Inc. System and method for fibrechannel fail-over through port spoofing
US20040233910A1 (en) * 2001-02-23 2004-11-25 Wen-Shyen Chen Storage area network using a data communication protocol
US7058788B2 (en) * 2001-02-23 2006-06-06 Falconstor Software, Inc. Dynamic allocation of computer memory
US7346783B1 (en) * 2001-10-19 2008-03-18 At&T Corp. Network security device and method
US7783901B2 (en) * 2001-12-05 2010-08-24 At&T Intellectual Property Ii, L.P. Network security device and method
US8983938B1 (en) * 2009-02-06 2015-03-17 Hewlett-Packard Development Company, L.P. Selecting a command file

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4458316A (en) * 1981-03-06 1984-07-03 International Business Machines Corporation Queuing commands in a peripheral data storage system
US4901232A (en) * 1983-05-19 1990-02-13 Data General Corporation I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor
EP0255090A3 (en) * 1986-07-28 1990-02-07 Honeywell Bull Inc. Lan controller proprietary bus
US5237659A (en) * 1989-07-27 1993-08-17 Bull S.A. Gateway device for connecting a computer bus to a ring network
JP2965043B2 (ja) * 1990-04-10 1999-10-18 三菱電機株式会社 デュアルポートメモリ
FR2679352B1 (fr) * 1991-07-15 1996-12-13 Bull Sa Dispositif universel de couplage d'un bus d'ordinateur a un controleur d'un groupe de peripheriques.

Also Published As

Publication number Publication date
DE69325135D1 (de) 1999-07-08
EP0588703B1 (fr) 1999-06-02
EP0588703A1 (fr) 1994-03-23
FR2695740A1 (fr) 1994-03-18
US5561812A (en) 1996-10-01
DE69325135T2 (de) 1999-10-28
FR2695740B1 (fr) 1994-11-25
JPH07120320B2 (ja) 1995-12-20
JPH06187267A (ja) 1994-07-08

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