ES2145755T3 - Desincronizador incremental de alisado de fase y aparato de calculo. - Google Patents

Desincronizador incremental de alisado de fase y aparato de calculo.

Info

Publication number
ES2145755T3
ES2145755T3 ES93112765T ES93112765T ES2145755T3 ES 2145755 T3 ES2145755 T3 ES 2145755T3 ES 93112765 T ES93112765 T ES 93112765T ES 93112765 T ES93112765 T ES 93112765T ES 2145755 T3 ES2145755 T3 ES 2145755T3
Authority
ES
Spain
Prior art keywords
synchronizer
synchronous communication
clock
branch
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93112765T
Other languages
English (en)
Inventor
William Edward Powell
William Bernard Weeber
Manal Elsayed Afify
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Nokia Inc
Original Assignee
Alcatel SA
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA, Nokia Inc filed Critical Alcatel SA
Application granted granted Critical
Publication of ES2145755T3 publication Critical patent/ES2145755T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored program control
    • H04Q11/0414—Details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0003—Switching fabrics, e.g. transport network, control network

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Water Treatment By Electricity Or Magnetism (AREA)
  • Treating Waste Gases (AREA)
  • Filtering Of Dispersed Particles In Gases (AREA)

Abstract

UN DESINCRONIZADOR (20) PARA DESINCRONIZAR DATOS ALMACENADOS DENTRO DE ENVOLTURAS DE CARGA SINCRONA DE UN PROTOCOLO DE COMUNICACION SINCRONA TAL COMO SONET (RED OPTICA SINCRONA), PREVE SUAVIZA LA SEÑAL DE RELOJ PERIODICAMENTE DISCONTINUA ASOCIADA CON TAL DATO DESPUES DE QUE EL PROTOCOLO DE COMUNICACION SINCRONO AEREO HAYA SIDO ELIMINADO. EL DESINCRONIZADOR ACOMODA PARA DESPLAZAMIENTO EN LA POSICION DE LA ENVOLTURA DE CARGA Y ASI ESOS DATOS DENTRO DEL MARCO DE COMUNICACION SINCRONA ASI COMO DENTRO AJUSTE DENTRO DE LOS DATOS EN SI DEBIDO A INFORMACION DE MATERIAL DE . EL DESINCRONIZADOR UTILIZA UN FILTRO DE FUGA 826) QUE TIENE UNA RAMA LINEAL (54) Y UNA RAMA INTEGRADOR (56), TENIENDO AMBAS RAMAS FACTORES AJUSTABLES (61, 63, 65, 88, 90,93, 95, 100, 102, 105) RESPECTO DE SU OPERACION, DONDE LOS FACTORES AJUSTABLES SE ELIGEN DEPENDIENDO DE LOS VALORES UMBRAL (86, 87, 89, 62) QUE A SU VEZ ESTAN BASADOS EN LA DIFERENCIA ENTRE LA DIRECCION EXRITA MEDIA Y LA DIRECCION LEIDA PARA EL ALMACEN ELASTICOASOCIADO (22) DENTRO DEL CUAL LOS DATOS ENTRANTES ELIMINADOS DEL MARCO DEL SISTEMA DE COMUNICACION SINCRONO SE ALMACENAN TEMPORALMENTE. EL FILTRO DE FUGA (26) FORMA PARTE DE UN BUCLE CERRADO DE FASE QUE A SU VEZ AJUSTA LA FRECUENCIA DE RELOJ LEIDA (46) DE MANERA A MINIMIZAR LA INUNDACION LA FALTA DE FLUJO DEL ALMACEN ELASTICO MIENTRAS QUE MINIMIZA SIMULTANEAMENTE LA VELOCIDAD DE CAMBIO DE LA VELOCIDAD DE RELOJ LEIDO DE MANERA A LIMITAR EL TEMBLOR. UN APARATO DE RECUPERACION DE FALLA FORMA PARTE DEL DESINCRONIZADOR PARA PERMITIR LOS FACTORES DE GANANCIA ALTA DE RELOJ RAPIDO (67, 97, 107) PARA AJUSTAR RAPIDAMENTE EL RELOJ DE LECTURA CUANDO OCURRE LA FALTA DE FLUJO O INUNDACION DE ALMACEN ELASTICO. EL FACTOR DE GANANCIA ASOCIADO A TANTO LA RAMA LINEAL COMO LA RAMA INTEGRADOR QUE PUEDE SER MODIFICADA PARA ENCONTRAR LA NECESIDAD DE TEMBLOR PARTICULAR DE UN SISTEMA DE COMUNICACION SINCRONO PARTICULAR. U APARATO DE CALCULO (82) REALIZA CALCULOS PARA GENERAR EL VALOR DE SALIDA DEL FILTRO DE FUGA QUE UTILIZA UN NUMERO REDUCIDO DE PUERTAS LOGICAS PARA LA IMPLEMENTACION ASIC.
ES93112765T 1992-08-25 1993-08-10 Desincronizador incremental de alisado de fase y aparato de calculo. Expired - Lifetime ES2145755T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/935,008 US5402452A (en) 1992-08-25 1992-08-25 Incremental phase smoothing desynchronizer and calculation apparatus

Publications (1)

Publication Number Publication Date
ES2145755T3 true ES2145755T3 (es) 2000-07-16

Family

ID=25466437

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93112765T Expired - Lifetime ES2145755T3 (es) 1992-08-25 1993-08-10 Desincronizador incremental de alisado de fase y aparato de calculo.

Country Status (6)

Country Link
US (2) US5402452A (es)
EP (1) EP0584627B1 (es)
AT (1) ATE192616T1 (es)
AU (2) AU667935B2 (es)
DE (1) DE69328521T2 (es)
ES (1) ES2145755T3 (es)

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US5630112A (en) * 1991-06-19 1997-05-13 Kabushiki Kaisha Toshiba System using timing information contained in data read from reproduction unit controlled by first oscillator to vary frequency of independent system clock signal
DE69429574T2 (de) * 1993-11-10 2002-09-26 Nortel Networks Ltd., St.Laurent Regelung des Ablaufs von Zeigeranpassungsereignissen
GB9323187D0 (en) * 1993-11-10 1994-01-05 Northern Telecom Ltd Pointer justification even leak control
IT1265424B1 (it) * 1993-12-22 1996-11-22 Alcatel Italia Metodo e disposizione ciruitale di realizzazione della funzione di hpa negli apparati sdh
JPH07245603A (ja) * 1994-01-11 1995-09-19 Fujitsu Ltd ジッタ抑圧制御方法およびその回路
ES2102938B1 (es) * 1994-03-28 1998-04-16 Alcatel Standard Electrica Sistema de reduccion de fluctuaciones de fase en demultiplexores digitales.
US5548534A (en) * 1994-07-08 1996-08-20 Transwitch Corporation Two stage clock dejitter circuit for regenerating an E4 telecommunications signal from the data component of an STS-3C signal
EP0727887B1 (de) * 1995-02-16 2002-08-28 Alcatel Stopfeinrichtung für synchrones digitales Übertragungssystem
US5781597A (en) * 1995-02-16 1998-07-14 Alcatel Sel Aktiengesellschaft Synchronous digital transmission system having justification circuit that counts frame bytes, calculates offsets, compares thresholds, and initiates justification action
GB2303981A (en) * 1995-07-29 1997-03-05 Northern Telecom Ltd Broadcast video desynchroniser
GB2312353B (en) * 1996-04-16 2000-12-06 Gpt Ltd Digital telecommunications transmision systems
US5793824A (en) * 1996-04-30 1998-08-11 Adtran, Inc. Digital phase locked loop having adaptive bandwidth for pulse stuffing synchronized digital communication system
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
US5898744A (en) * 1996-10-07 1999-04-27 Motorola, Inc. Apparatus and method for clock recovery in a communication system
US6088413A (en) * 1997-05-09 2000-07-11 Alcatel Apparatus for reducing jitter in a desynchronizer
DE19740107A1 (de) 1997-09-12 1999-03-18 Alsthom Cge Alcatel Verfahren zum Übertragen von Datenpaketen und zur Durchführung des Verfahrens geeignetes Netzelement
US6111878A (en) * 1997-11-04 2000-08-29 Alcatel Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads
DE19820572A1 (de) * 1998-05-08 1999-11-11 Alcatel Sa Desynchronisiereinrichtung für ein synchrones digitales Nachrichtenübertragungssystem
IT1307715B1 (it) * 1999-09-30 2001-11-14 Cit Alcatel Circuito di desincronizzazione di flussi tributari in trame didivisione di tempo in reti di telecomunicazioni e relativo metodo.
EP1091289B1 (en) 1999-10-08 2004-05-26 Hewlett-Packard Company, A Delaware Corporation Device for processing sonet or SDH frames-DS0 to channel mapping
EP1091288A1 (en) * 1999-10-08 2001-04-11 Hewlett-Packard Company Device for processing sonet or SDH frames having an H.100 bus
CN1307406A (zh) * 2000-01-27 2001-08-08 华为技术有限公司 数字锁相环的滤波方法
CA2307044A1 (en) * 2000-04-28 2001-10-28 Pmc-Sierra Inc. Multi-channel sonet/sdh desynchronizer
US6819725B1 (en) * 2000-08-21 2004-11-16 Pmc-Sierra, Inc. Jitter frequency shifting Δ-Σ modulated signal synchronization mapper
SE0004303D0 (sv) * 2000-11-23 2000-11-23 Net Insight Ab Switching apparatus
US20020172310A1 (en) * 2001-05-18 2002-11-21 Manop Thamsirianunt Jitter attenuator fifo overflow-underflow protection using digital-phase locked loop's bandwidth adaptation
US6882662B2 (en) * 2001-06-07 2005-04-19 Applied Micro Circuits Corporation Pointer adjustment wander and jitter reduction apparatus for a desynchronizer
US6531926B1 (en) * 2001-09-13 2003-03-11 Overture Networks, Inc. Dynamic control of phase-locked loop
WO2004043011A1 (en) * 2002-11-06 2004-05-21 Wuhan Fiberhome Networks Co., Ltd. Multiple service ring of n-ringlet structure based on multiple fe, ge and 10ge
US6762649B2 (en) * 2002-11-27 2004-07-13 Broadcom Corporation System and method for automatic parameter adjustment within a phase locked loop system
US8019035B2 (en) * 2003-08-05 2011-09-13 Stmicroelectronics Nv Noise shaped interpolator and decimator apparatus and method
CN1848717B (zh) * 2005-04-15 2011-04-06 华为技术有限公司 获得异步解映射时钟的方法及电路
US7328114B2 (en) * 2005-12-09 2008-02-05 General Electric Company Methods and systems for measuring a rate of change of frequency
US8862797B2 (en) 2011-10-18 2014-10-14 Cortina Systems, Inc. Reducing delay and delay variation in a buffer in network communications

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US3564226A (en) * 1966-12-27 1971-02-16 Digital Equipment Parallel binary processing system having minimal operational delay
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Also Published As

Publication number Publication date
AU4444196A (en) 1996-06-13
EP0584627B1 (en) 2000-05-03
US5402452A (en) 1995-03-28
US5528530A (en) 1996-06-18
AU4463593A (en) 1994-03-03
AU692347B2 (en) 1998-06-04
ATE192616T1 (de) 2000-05-15
DE69328521T2 (de) 2001-03-15
EP0584627A3 (en) 1996-05-29
EP0584627A2 (en) 1994-03-02
DE69328521D1 (de) 2000-06-08
AU667935B2 (en) 1996-04-18

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